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The saying “round pegs do not fit square holes” persists because it captures a deep engineering reality: inefficiency most often arises not from flawed components, but from misalignment between a system’s assumptions and the problem it is asked to solve. A square hole is not poorly made; it’s simply optimized for square pegs.

Modern large language models (LLMs) now find themselves in exactly this situation. Although they are overwhelmingly executed on general-purpose graphics processing units (GPGPUs), these processors were never shaped around the needs of enormous inference-based matrix multiplications.

GPUs dominate not because they are a perfect match, but because they were already available, massively parallel, and economically scalable when deep learning began to grow, especially for training AI models.

What follows is not an indictment of GPUs, but a careful explanation of why they are extraordinarily effective when the workload is rather dynamic and unpredictable, such as graphic processing, and disappointedly inefficient when the workload is essentially regular and predictable, such as AI/LLM inference execution.

The inefficiencies that emerge are not accidental; they are structural, predictable, and increasingly expensive as models continue to evolve.

Execution geometry and the meaning of “square”

When a GPU renders a graphic scene, it deals with a workload that is considerably irregular at the macro level, but rather regular at the micro level. A graphic scene changes in real time with significant variations in content—changes in triangles and illumination—but in an image, there is usually a lot of local regularity.

One frame displays a simple brick wall, the next, an explosion creating thousands of tiny triangles and complex lighting changes. To handle this, the GPU architecture relies on a single-instruction multiple threads (SIMT) or wave/warp-based approach where all threads in a “wave” or “warp,” usually between 16 and 128, receive the same instruction at once.

This works rather efficiently for graphics because, while the whole scene is a mess, local patches of pixels are usually doing the same thing. This allows the GPU to be a “micro-manager,” constantly and dynamically scheduling these tiny waves to react to the scene’s chaos.

However, when applied to AI and LLMs, the workload changes entirely. AI processing is built on tensor math and matrix multiplication, which is fundamentally regular and predictable. Unlike a highly dynamic game scene, matrix math is just an immense but steady flow of numbers. Because AI is so consistent, the GPU’s fancy, high-speed micro-management becomes unnecessary. In this context, that hardware is just “overhead,” consuming power and space for a flexibility that the AI doesn’t actually use.

This leaves the GPGPU in a bit of a paradox: it’s simultaneously too dynamic and not dynamic enough. It’s too dynamic because it wastes energy on micro-level programming and complex scheduling that a steady AI workload doesn’t require. Yet it’s not dynamic enough because it is bound by the rigid size of its “waves.”

If the AI math doesn’t perfectly fit into a warp of 32, the GPU must use “padding,” effectively leaving seats empty on the bus. While the GPU is a perfect match for solving irregular graphics problems, it’s an imperfect fit for the sheer, repetitive scale of modern tensor processing.

Wasted area as a physical quantity

This inefficiency can be understood geometrically. A circle inscribed in a square leaves about 21% of the square’s area unused. In processing hardware terms, the “area” corresponds to execution lanes, cycles, bandwidth, and joules. Any portion of these resources that performs work that does not advance the model’s output is wasted area.

The utilization gap (MFU)

The primary way to quantify this inefficiency is through Model FLOPs Utilization (MFU). This metric measures how much of the chip’s theoretical peak math power is actually being used for the model’s calculations versus how much is wasted on overhead, data movement, or idling.

For an LLM like GPT-4 running on GPGPT-based accelerators operating in interactive mode, the MFU drops by an order of magnitude with the hardware busy with “bookkeeping,” which encompasses moving data between memory levels, managing thread synchronization, or waiting for the next “wave” of instructions to be decoded.

The energy cost of flexibility

The inefficiency is even more visible in power consumption. A significant portion of that energy is spent powering the “dynamic micromanagement,” namely, the logic gates that handle warp scheduling, branch prediction, and instruction fetching for irregular tasks.

The “padding” penalty

Finally, there is the “padding” inefficiency. Because a GPGPU-based accelerator operates in fixed wave sizes (typically 32 or 64 threads), if the specific calculation doesn’t perfectly align with those multiples, often happening in the “Attention” mechanism of the LLM model, the GPGPU still burns the power for a full wave while some threads sit idle.

These effects multiply rather than add. A GPU may be promoted with a high throughput, but once deployed, may deliver only a fraction of its peak useful throughput for LLM inference, while drawing close to peak power.

The memory wall and idle compute

Even if compute utilization was perfect, LLM inference would still collide with the memory wall, the growing disparity between how fast processors can compute and how fast they can access memory. LLM inference has low arithmetic intensity, meaning that relatively few floating-point operations are performed per byte of data fetched. Much of the execution time is spent reading and writing the key-value (KV) cache.

GPUs attempt to hide memory latency using massive concurrency. Each streaming multiprocessor (SM) holds many warps and switches between them while others wait for memory. This strategy works well when memory accesses are staggered and independent. In LLM inference, however, many warps stall simultaneously while waiting for similar memory accesses.

As a result, SMs spend large fractions of idle time, not because they lack instructions, but because data cannot arrive fast enough. Measurements commonly show that 50–70% of cycles during inference are lost to memory stalls. Importantly, the power draw does not scale down proportionally since clocks continue toggling and control logic remains active, resulting in poor energy efficiency.

Predictable stride assumptions and the cost of generality

To maximize bandwidth, GPUs rely on predictable stride assumptions; that is, the expectation that memory accesses follow regular patterns. This enables techniques such as cache line coalescing and memory swizzling, a remapping of addresses designed to avoid bank conflicts and improve locality.

LLM memory access patterns violate these assumptions. Accesses into the KV cache depend on token position, sequence length, and request interleaving across users. The result is reduced cache effectiveness and increased pressure on address-generation logic. The hardware expends additional cycles and energy rearranging data that cannot be reused.

This is often described as a “generality tax.”

Why GPUs still dominate

Given these inefficiencies, it’s natural to ask why GPUs remain dominant. The answer lies in history rather than optimality. Early deep learning workloads were dominated by dense linear algebra, which mapped reasonably well onto GPU hardware. Training budgets were large enough that inefficiency could be absorbed.

Inference changes priorities. Latency, cost per token, and energy efficiency now matter more than peak throughput. At this stage, structural inefficiencies are no longer abstract; they directly translate into operational cost.

From adapting models to aligning hardware

For years, the industry focused on adapting models to hardware such as larger batches, heavier padding, and more aggressive quantization. These techniques smooth the mismatch but do not remove it.

A growing alternative is architectural alignment: building hardware whose execution model matches the structure of LLMs themselves. Such designs schedule work around tokens rather than warps, and memory systems are optimized for KV locality instead of predictable strides. By eliminating unused execution lanes entirely, these systems reclaim the wasted area rather than hiding it.

The inefficiencies seen in modern AI data centers—idle compute, memory stalls, padding overhead, and excess power draw—are not signs of poor engineering. They are the inevitable result of forcing a smooth, temporal workload into a rigid, geometric execution model.

GPUs remain masterfully engineered square holes. LLMs remain inherently round pegs. As AI becomes a key ingredient in global infrastructure, the cost of this mismatch becomes the problem itself. The next phase of AI computing will belong not to those who shave the peg more cleverly, but to those who reshape the hole to match the true geometry of the workload.

Lauro Rizzatti is a business advisor to VSORA, a technology company offering silicon semiconductor solutions that redefine performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Special Section: AI Design

• The AI design world in 2026: What you need to know
• AI workloads demand smarter SoC interconnect design
• AI’s insatiable appetite for memory
• The AI-tuned DRAM solutions for edge AI workloads
• Designing edge AI for industrial applications

The post Round pegs, square holes: Why GPGPUs are an architectural mismatch for modern LLMs appeared first on EDN.

The versatility of the venerable LMC555 CMOS analog timer is so well known it’s virtually a cliche, but sometimes it can still surprise us.  The circuit in Figure 1 is an example.  In it a single linear pot in a simple RC network sets the frequency of 555 square wave oscillation over a greater than 10 Hz to 100 kHz range, exceeding a 10,000:1 four decade, thirteen octave ratio.  Here’s how it works.

Figure 1 R1 sets U1 frequency from < 10Hz to > 100kHz.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Potentiometer R1 provides variable attenuation of U1’s 0 to V+ peak-to-peak square wave output to the R4R5C1 divider/integrator.  The result is a sum of an abbreviated timing ramp component developed by C1 sitting on top of an attenuated square wave component developed by R5.  This composite waveshape is input to the Trigger and Threshold pins of U1, resulting in the frequency vs R1 position function plotted on Figure 2′s semi-log graph.

Figure 2 U1 oscillation range vs R1 setting is so wide it needs a log scale to accommodate it.

Curvature of the function does get pretty radical as R1 approaches its limits of travel. Nevertheless,  log conformity is fairly decent over the middle 10% to 90% of the pot’s travel and the resulting 2 decades of frequency range. This is sketched in red in Figure 3.

Figure 3 Reasonably good log conformity is seen over mid-80% of R1’s travel.

Of course, as R1 is dialed to near its limits, frequency precision (or lack of it) becomes very sensitive to production tolerances in U1’s internal voltage divider network and those of the circuits external resistors. 

This is why U1’s frequency output is taken from pin 7 (Discharge) instead of pin 3 (Output) to at least minimize the effects of loading from making further contributions to instability.

Nevertheless, the strong suit of this design is definitely its dynamic range.  Precision?  Not so much.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Another weird 555 ADC
• Gated 555 astable hits the ground running
• More gated 555 astable multivibrators hit the ground running
• Inverted MOSFET helps 555 oscillator ignore power supply and temp variations

 

The post Tune 555 frequency over 4 decades appeared first on EDN.

Battery energy storage systems (BESSes) are increasingly being adopted to improve efficiency and stability in power distribution networks. By storing energy from both renewable sources, such as solar and wind, and the conventional power grid, BESSes balance supply and demand, stabilizing power grids and optimizing energy use.

This article examines emerging trends in BESS applications, including advances in battery technologies, the development of hybrid energy storage systems (HESSes), and the introduction of AI-based solutions for optimization.

Battery technologies

Lithium-ion (Li-ion) is currently the main battery technology used in BESSes. Despite the use of expensive raw materials, such as lithium, cobalt, and nickel, the global average price of Li-ion battery packs has declined in 2025.

BloombergNEF reports that Li-ion battery pack prices have fallen to a new low this year, reaching $108/kWh, an 8% decrease from the previous year. The research firm attributes this decline to excess cell manufacturing capacity, economies of scale, the increasing use of lower-cost lithium-iron-phosphate (LFP) chemistries, and a deceleration in the growth of electric-vehicle sales.

Using iron phosphate as the cathode material, LFP batteries achieve high energy density, long cycle life, and good performance at high temperatures. They are often used in applications in which durability and reliable operation under adverse conditions are important, such as grid energy storage systems. However, their energy density is lower than that of traditional Li-ion batteries.

Although Li-ion batteries will continue to lead the BESS market due to their higher efficiency, longer lifespan, and deeper depth of discharge compared with alternative battery technologies, other chemistries are making progress.

Flow batteries

Long-life storage systems, capable of storing energy for eight to 10 hours or more, are suited for managing electricity demand, reducing peaks, and stabilizing power grids. In this context, “reduction-oxidation [redox] flow batteries” show great promise.

Unlike conventional Li-ion batteries, the liquid electrolytes in flow batteries are stored separately and then flow (hence the name) into the central cell, where they react in the charging and discharging phases.

Flow batteries offer several key advantages, particularly for grid applications with high shares of renewables. They enable long-duration energy storage, covering many hours, such as nighttime, when solar generation is not present. Their raw materials, such as vanadium, are generally abundant and face limited supply constraints. Material concerns are further mitigated by high recyclability and are even less significant for emerging iron-, zinc-, or organic-electrolyte technologies.

Flow batteries are also modular and compact, inherently safe due to the absence of fire risk, and highly durable, with service lifetimes of at least 20 years with minimal performance degradation.

The BESSt Company, a U.S.-based startup founded by a former Tesla engineer, has unveiled a redox flow battery technology that is claimed to achieve an energy density up to 20× higher than that of traditional, vanadium-based flow storage systems.

The novel technology relies on a zinc-polyiodide (ZnI2) electrolyte, originally developed by the U.S. Department of Energy’s Pacific Northwest National Laboratory, as well as a proprietary cell stack architecture that relies on undisclosed, Earth-abundant alloy materials sourced domestically in the U.S.

The company’s residential offering is designed with a nominal power output of 20 kW, paired with an energy storage capacity of 25 kWh, corresponding to an average operational duration of approximately five hours. For commercial and industrial applications, the proposed system is designed to scale to a power rating of 40 kW and an energy capacity of 100 kWh, enabling an average usage time of approximately 6.5 hours.

This technology (Figure 1) is well-suited for integration with solar generation and other renewable energy installations, where it can deliver long-duration energy storage without performance degradation.

Figure 1: The BESSt Company’s ZnI2 redox flow battery system (Source: The BESSt Company) Sodium-ion batteries

Sodium-ion batteries are a promising alternative to Li-ion batteries, primarily because they rely on more abundant raw materials. Sodium is widely available in nature, whereas lithium is relatively scarce and subject to supply chains that are vulnerable to price volatility and geopolitical constraints. In addition, sodium-ion batteries use aluminum as a current collector instead of copper, further reducing their overall cost.

Blue Current, a California-based company specializing in solid-state batteries, has received an $80 million Series D investment from Amazon to advance the commercialization of its silicon solid-state battery technology for stationary storage and mobility applications. The company aims to establish a pilot line for sodium-ion battery cells by 2026.

Its approach leverages Earth-abundant silicon and elastic polymer anodes, paired with fully dry electrolytes across multiple formulations optimized for both stationary energy storage and mobility. Blue Current said its fully dry chemistry can be manufactured using the same high-volume equipment employed in the production of Li-ion pouch cells.

Sodium-ion batteries can be used in stationary energy storage, solar-powered battery systems, and consumer electronics. They can be transported in a fully discharged state, making them inherently safer than Li-ion batteries, which can suffer degradation when fully discharged.

Aluminum-ion batteries

Project INNOBATT, coordinated by the Fraunhofer Institute for Integrated Systems and Device Technology (IISB), has completed a functional battery system demonstrator based on aluminum-graphite dual-ion batteries (AGDIB).

Rechargeable aluminum-ion batteries represent a low-cost and inherently non-flammable energy storage approach, relying on widely available materials such as aluminum and graphite. When natural graphite is used as the cathode, AGDIB cells reach gravimetric energy densities of up to 160 Wh/kg while delivering power densities above 9 kW/kg. The electrochemical system is optimized for high-power operation, enabling rapid charge and discharge at elevated C rates and making it suitable for applications requiring a fast dynamic response.

In the representative system-level test (Figure 2), the demonstrator combines eight AGDIB pouch cells with a wireless battery management system (BMS) derived from the open-source foxBMS platform. Secure RF communication is employed in conjunction with a high-resolution current sensor based on nitrogen-vacancy centers in diamond, enabling precise current measurement under dynamic operating conditions.

Figure 2: A detailed block diagram of the INNOBATT battery system components (Source: Elisabeth Iglhaut/Fraunhofer IISB) Li-ion battery recycling

Second-life Li-ion batteries retired from applications such as EVs often maintain a residual storage capacity and can therefore be repurposed for BESSes, supporting circular economy standards. In Europe, the EU Battery Passport—mandatory beginning in 2027 for EV, industrial, BESS (over 2 kWh), and light transport batteries—will digitally track batteries by providing a QR code with verified data on their composition, state of health, performance (efficiency, capacity), and carbon footprint.

This initiative aims to create a circular economy, improving product sustainability, transparency, and recyclability through digital records that detail information about product composition, origin, environmental impact, repair, and recycling.

HESSes

A growing area of innovation is represented by the HESS, which integrates batteries with alternative energy storage technologies, such as supercapacitors or flywheels. Batteries offer high energy density but relatively low power density, whereas flywheels and supercapacitors provide high power density for rapid energy delivery but store less energy overall.

By combining these technologies, HESSes can better balance both energy and power requirements. Such systems are well-suited for applications such as grid and microgrid stabilization, as well as renewable energy installations, particularly solar and wind power systems.

Utility provider Rocky Mountain Power (RMP) and Torus Inc., an energy storage solutions company, are collaborating on a major flywheel and BESS project in Utah. The project integrates Torus’s mechanical flywheel technology with battery systems to support grid stability, demand response, and virtual power plant applications.

Torus will deploy its Nova Spin flywheel-based energy storage system (Figure 3) as part of the project. Flywheels operate using a large, rapidly spinning cylinder enclosed within a vacuum-sealed structure. During charging, electrical energy powers a motor that accelerates the flywheel, while during discharge, the same motor operates as a generator, converting the rotational energy back into electricity. Flywheel systems offer advantages such as longer lifespans compared with most chemical batteries and reduced sensitivity to extreme temperatures.

This collaboration is part of Utah’s Operation Gigawatt initiative, which aims to expand the state’s power generation capacity over the next decade. By combining the rapid response of flywheels with the longer-duration storage of batteries, the project delivers a robust hybrid solution designed for a service life of more than 25 years while leveraging RMP’s Wattsmart Battery program to enhance grid resilience.

Figure 3: Torus Nova Spin flywheel-based energy storage (Source: Torus Inc.) AI adoption in BESSes

By utilizing its simulation and testing solution Simcenter, Siemens Digital Industries Software demonstrates how AI reinforcement learning (RL) can help develop more efficient, faster, and smarter BESSes.

The primary challenge of managing renewable energy sources, such as wind power, is determining the optimal charge and discharge timing based on dynamic variables such as real-time electricity pricing, grid load conditions, weather forecasts, and historical generation patterns.

Traditional control systems rely on simple, manually entered rules, such as storing energy when prices fall below weekly averages and discharging when prices rise. On the other hand, RL is an AI approach that trains intelligent agents through trial and error in simulated environments using historical data. For BESS applications, the RL agent learns from two years of weather patterns to develop sophisticated control strategies that provide better results than manual programming capabilities.

The RL-powered smart controller continuously processes wind speed forecasts, grid demand levels, and market prices to make informed, real-time decisions. It learns to charge batteries during periods of abundant wind generation and low prices, then discharge during demand spikes and price peaks.

The practical implementation of Siemens’s proposed approach combines system simulation tools to create digital twins of BESS infrastructure with RL training environments. The resulting controller can be deployed directly to hardware systems.

The post Emerging trends in battery energy storage systems appeared first on EDN.

Industrial manufacturing systems demand real-time decision-making, adaptive control, and autonomous operation. However, many cloud-dependent architectures can’t deliver the millisecond response required for safety-critical functions such as robotic collision avoidance, in-line quality inspection, and emergency shutdown.

Network latency (typically 50–200 ms round-trip) and bandwidth constraints prevent cloud processing from achieving sub-10 ms response requirements, shifting intelligence to the industrial edge for real-time control.

Edge AI addresses these high-performance, low-latency requirements by embedding intelligence directly into industrial devices and enabling local processing without reliance on the cloud. This edge-based approach supports machine-vision workloads for real-time defect detection, adaptive process control, and responsive human–machine interfaces that react instantly to dynamic conditions.

This article outlines a comprehensive approach to designing edge AI systems for industrial applications, covering everything from requirements analysis to deployment and maintenance. It highlights practical design methodologies and proven hardware platforms needed to bring AI from prototyping to production in demanding environments.

Defining industrial requirements

Designing scalable industrial edge AI systems begins with clearly defining hardware, software, and performance requirements. Manufacturing environments necessitate wide temperature ranges from –40°C to +85°C, resistance to vibration and electromagnetic interference (EMI), and zero tolerance for failure.

Edge AI hardware installed on machinery and production lines must tolerate these conditions in place, unlike cloud servers operating in climate-controlled environments.

Latency constraints are equally demanding: robotic assembly lines require inference times under 10 milliseconds for collision avoidance and motion control, in-line inspection systems must detect and reject defective parts in real time, and safety interlocks depend on millisecond-level response to protect operators and equipment.

Figure 1 Robotic assembly lines require inference times under 10 milliseconds for collision avoidance and motion control. Source: Infineon

Accuracy is also critical, with quality control often targeting greater than 99% defect detection, and predictive maintenance typically aiming for high-90s accuracy while minimizing false alarm rates.

Data collection and preprocessing

Meeting these performance standards requires systematic data collection and preprocessing, especially when defect rates fall below 5% of samples. Industrial sensors generate diverse signals such as vibration, thermal images, acoustic traces, and process parameters. These signals demand application-specific workflows to handle missing values, reduce dimensionality, rebalance classes, and normalize inputs for model development.

Continuous streaming of raw high-resolution sensor data can exceed 100 Mbps per device, which is unrealistic for most factory networks. As a result, preprocessing must occur at the industrial edge, where compute resources are located directly on or near the equipment.

Class-balancing techniques such as SMOTE or ADASYN address class imbalance in training data, with the latter adapting to local density variations. Many applications also benefit from domain-specific augmentation, such as rotating thermal images to simulate multiple views or injecting controlled noise into vibration traces to reflect sensor variability.

Outlier detection is equally important, with clustering-based methods flagging and correcting anomalous readings before they distort model training. Synthetic data generation can introduce rare events such as thermal hotspots or sudden vibration spikes, improving anomaly detection when real-world samples are limited.

With cleaner inputs established, focus shifts to model design. Convolutional neural networks (CNNs) handle visual inspection, while recurrent neural networks (RNNs) process time-series data. Transformers, though still resource-intensive, increasingly perform industrial time-series analysis. Efficient execution of these architectures necessitates careful optimization and specialized hardware support.

Hardware-accelerated processing

Efficient edge inference requires optimized machine learning models supported by hardware that accelerates computation within strict power and memory budgets. These local computations must stay within typical power envelopes below 5 W and operate without network dependency, which cloud-connected systems can’t guarantee in production environments.

Training neural networks for industrial applications can be challenging, especially when processing vibration signals, acoustic traces, or thermal images. Traditional workflows require data science expertise to select model architectures, tune hyperparameters, and manage preprocessing steps.

Even with specialized hardware, deploying deep learning models at the industrial edge demands additional optimization. Compression techniques shrink models by 80–95% while retaining over 95% accuracy, reducing size and accelerating inference to meet edge constraints. These include:

• Quantization converts 32-bit floating-point models into 8- or 16-bit integer formats, reducing memory use and accelerating inference. Post-training quantization meets most industrial needs, while quantization-aware training maintains accuracy in safety-critical cases.
• Pruning removes redundant neural connections, typically reducing parameters by 70–90% with minimal accuracy loss. Overparameterized models, especially those trained on smaller industrial datasets, benefit significantly from pruning.
• Knowledge distillation trains a smaller student model to replicate the behavior of a larger teacher model, retaining accuracy while achieving the efficiency required for edge deployment.

Deployment frameworks and tools

After compression and optimization, engineers deploy machine learning models using inference frameworks, such as TensorFlow Lite Micro and ExecuTorch, which are the industry standards. TensorFlow Lite Micro offers hardware acceleration through its delegate system, which is especially useful on platforms with supported specialized processors.

While these frameworks handle model execution, scaling from prototype to production also requires integration with development environments, control interfaces, and connectivity options. Beyond toolchains, dedicated development platforms further streamline edge AI workflows.

Once engineers develop and deploy models, they test them under real-world industrial conditions. Validation must account for environmental variation, EMI, and long-term stability under continuous operation. Stress testing should replicate production factors such as varying line speeds, material types, and ambient conditions to confirm consistent performance and response times across operational states.

Industrial applications also require metrics beyond accuracy. Quality inspection systems must balance false positives against false negatives, where the geometric mean (GM) provides a balanced measure on imbalanced datasets common in manufacturing. Predictive maintenance workloads rely on indicators such as mean time between false positives (MTBFP) and detection latency.

Figure 2 Quality inspection systems must balance false positives against false negatives. Source: Infineon

Validated MCU-based deployments demonstrate that optimized inference—even under resource constraints—can maintain near-baseline accuracy with minimal loss.

Monitoring and maintenance strategies

Validation confirms performance before deployment, yet real-world operation requires continuous monitoring and proactive maintenance. Edge deployments demand distributed monitoring architectures that continue functioning offline, while hybrid edge-to-cloud models provide centralized telemetry and management without compromising local autonomy.

A key focus of monitoring is data drift detection, as input distributions can shift with tool wear, process changes, or seasonal variation. Monitoring drift at both device and fleet levels enables early alerts without requiring constant cloud connectivity. Secure over-the-air (OTA) updates extend this framework, supporting safe model improvements, updates, and bug fixes.

Features such as secure boot, signed updates, isolated execution, and secure storage ensure only authenticated models run in production, helping manufacturers comply with regulatory frameworks such as the EU Cyber Resilience Act.

Take, for instance, an industrial edge AI case study about predictive maintenance. A logistics operator piloted edge AI silicon on a fleet of forklifts, enabling real-time navigation assistance and collision avoidance in busy warehouse environments.

The deployment reduced safety incidents and improved route efficiency, achieving better ROI. The system proved scalable across multiple facilities, highlighting how edge AI delivers measurable performance, reliability, and efficiency gains in demanding industrial settings.

The upgraded forklifts highlighted key lessons for AI at the edge: systematic data preprocessing, balanced model training, and early stress testing were essential for reliability, while underestimating data drift remained a common pitfall.

Best practices included integrating navigation AI with existing fleet management systems, leveraging multimodal sensing to improve accuracy, and optimizing inference for low latency in real-time safety applications.

Sam Al-Attiyah is head of machine learning at Infineon Technologies.

Special Section: AI Design

• The AI design world in 2026: What you need to know
• AI workloads demand smarter SoC interconnect design
• AI’s insatiable appetite for memory
• The AI-tuned DRAM solutions for edge AI workloads

The post Designing edge AI for industrial applications appeared first on EDN.

A recent Design Idea (DI), “Silly simple precision 0/20mA to 4/20mA converter,” by prolific DI contributor Stephen Woodward uses the venerable LM337 regulator in a creative configuration along with a few passive components, to translate an input 0-20 mA current source (say from a sensor with a separate power source that outputs a 0-20 mA signal current) into a 4-20 mA two-wire transmitter current loop (a standard 2 terminal industrial current source).

Below is another novel, ‘silly simple’ way of implementing the same function using the LM337. It relies on tapering off an initial 4 mA current to zero in proportion to the input 0-20 mA, and adding the input and the tapered off 4mA signal to create a 2-wire 4-20 mA output loop. It is loosely based on another Woodward gem [3]. Refer to Figure 1.

Figure 1 An input 0-20 mA is added to a tapered-off 4-0 mA at OUT to give an output 4-20 mA.

Wow the engineering world with your unique design: Design Ideas Submission Guide

First, imagine ‘0 mA’ current input (input loop open). The series arrangement of R1 parallel ‘R2 + Pz’ (‘Rz’@250E) and R3 parallel ‘R4+Ps’ (‘Rs’@62.5E) having a nominal value of 312.5E, sets the value of output loop current into OUT at 0mA+4mA (1.25V/312.5E), set using Pz.

Now, feeding a 20mA input current, imagine it pulled from junction X and pushed into the OUT terminal. This current is sourced from the output loop ‘+’, dropping 62.5E x 20mA=1.25V in Rs, in a direction opposing the internal reference voltage. With proper calibration, this reduces the drop across Rz to zero, and in doing so, reduces the original 4 mA contribution through Rz into OUT, also to zero.

The output loop current is now equal to the input current of 20mA+0mA (added at OUT), transferred from the input loop to the output loop from OUT to IN of U1. We have converted a current source input of 0-20 mA to a 2-wire loop current of 4-20 mA. The 20 mA setting is done by Ps.

Accurate current setting requires 2 S/Z passes to set the output current to within 0.05% or (much) better. Pots should be multi turn 3296 types or similar, but single turn trimmers will also work fairly well as both pots have a small trim range, by design.

The performance is excellent. The input to output linearity of the basic circuit is 0.02%. With a small heat sink, short term stability is within 0.02%, and change in loop current is 0.05% over a voltage from 5 V to 32 V. Transfer accuracy and stability are high because we aren’t transforming the input signal, only transferring it into the output loop. Reference drift affects only the basic 4 mA current and thus has a smaller effect on overall drift. The heat sink improves drift and di/dv by a factor of 3 to 4.

For intermediate input currents, the 4mA basic current via Rz into OUT is tapered off in proportion to the input 0-20 mA current. Thus at 10 mA (half) input current, the voltage at X changes suitably to maintain @500 mV across Rz, this supporting a contribution of 2 mA into OUT, down from the original 4 mA set at 0 mA input current. Output loop current into OUT is now the input 10mA+2mA=12mA, the halfway point of the 4-20 mA loop too. Similar reasoning applies to other input/output loop currents relationships.

A reverse protection diode is recommended in the 4-20 mA loop. Current limiting should be applied to limit fault current to safe levels. A series 2-transistor current limiter with appropriate resistance values is an excellent candidate, being low drop, low cost, fast acting and free from oscillation. A 40-mA ptc ‘polyfuse’ in the loop will protect the load from a complete short across both circuits (an unlikely event).

The basic drop seen by the 0-20 mA signal is -1 V to 0 V. Two diodes or an LED in series with the + of the 0-20-mA input allow the source to always see a positive drop.

Regarding stability: only the 68E(R3) and the 270E(R1) need to be 25 ppm 1% types to give low overall temperature drift, which is a significant plus. Pot drift, typically larger than that of fixed resistors, has less effect in the configuration used, wherein pots Ps and Pz, relatively high valued, control only a small part of the main current. Larger pot values also help minimize the effect of varying pot contact resistance.

A 3-V minimum operating voltage allows as much as 1000E of loop resistance with a 24-V supply, for the basic circuit.

It is a given that one of the loops will (need to) be floating. This is usually the source loop, as the instrument generating the 0-20 mA is powered from a separate supply.

Ashutosh Sapre lives and works in a large city in western India. Drifting uninspired through an EE degree way back in the late nineteen eighties, he was lucky enough to stumble across and be electrified by the Art of Electronics 1 and 2. Cut to now, he is a confirmed circuit addict, running a business designing, manufacturing and selling industrial signal processing modules. He is proud of his many dozens of design pads consisting mostly of crossed out design ideas.

Related Content/References

1. Silly simple precision 0/20mA to 4/20mA converter
2. A 0-20mA source current to 4-20mA loop current converter
3. PWM-programmed LM317 constant current source
4. https://www.radiolocman.com/shem/schematics.html?di=150983

The post Another silly simple precision 0/20mA to 4/20mA converter appeared first on EDN.

Satellites in geostationary orbit (GEO) face a harsher environment due to plasma, trapped electrons, solar particles, and cosmic rays, with the environmental effect higher in magnitude compared with low Earth orbit (LEO)-Low Inclination, LEO-Polar, and International Space Station orbits. This is the primary reason why power supplies used in these satellites need to comply with stringent MIL standards for design, manufacturability, and quality.

GEO satellites circle around the earth in approximately 24 hours at about 3 km/s, at an altitude of about 35,786 km. There are only three main satellites that can cover the full globe, as these satellites are far from Earth.

In comparison, LEO satellites travel around the earth at of 7.8 km/s, at an altitude of less than 1,000 km, but they could be as low as 160 km above Earth. This is lower than GEO but still >10× higher than a commercial plane altitude at 14 km.

Total ionizing dose (TID) and single-event effects (SEEs) are two of the key radiation effects that need to be addressed by power supplies in space. Satellites placed in GEO face harsher conditions due to radiation compared with those in LEO.

GEO being farther from Earth is more susceptible to radiation; hence, the components used in GEO satellite power supplies need to be radiation-hardened (rad-hard) by design, which means all of the components must comply with TID and SEEs, as high as 100 Krad and 82 MeV cm2/mg, respectively.

In comparison, the LEO satellite components need to be radiation-tolerant with a relatively lower level of requirement of TID and SEEs. However, using no shielding from these harsh conditions may result in failure.

While individual satellites can be used for higher-resolution imaging, typically constellations of a large number of exact or similar types of relatively smaller satellites form a web or net around the earth to provide uninterrupted coverage. By working in tandem, these constellations provide simultaneous coverage for applications such as internet services and telecommunication.

The emergence of New Space has enabled the launch of multiple smaller satellites with lighter payloads for commercial purposes. Satellite internet services are slowly and steadily competing with traditional broadband and are providing more reliable connectivity for remote areas, passenger vehicles, and even aerospace.

Microchip offers a scalable approach to space solutions based on the mission. (Source: Microchip Technology Inc.) Configurability for customization

The configurability of power supplies is an important factor for meeting a variety of space mission specifications. Voltage levels in the electrical power bus are generally standardized to certain values; however, the voltage of the solar array is not always standardized. This calls for a redesign of all the converters in the power subsystems, depending on the nature of the mission.

This redesign increases costs and development time. Thus, it is inherently important to provide DC/DC converters and low-dropout regulators (LDOs) across the power architecture that have standard specifications while providing the flexibility for customization depending on the system and load voltages. Functions such as paralleling, synchronization, and series connection are of paramount importance for power supplies when considering the specifications of different space missions.

Size, weight, power, and cost

Due to the limited volume available and the resource-intensive task of sending the objects into space against the pull of gravity, it is imperative to have smaller footprints, smaller size (volume), and lower weight while packing more power (kilowatts) in the given volume. This calls for higher power density for space optimization and higher efficiency (>80%) to get the maximum performance out of the resources available in the power system.

The load regulations need to be optimal to make sure that the output of the DC/DC converter feeds the next stage (LDOs and direct loads), matching the regulation requirements. Additionally, the tolerances of regulation against temperature variations are key in providing ruggedness and durability.

Space satellites use solar energy as the main source to power their loads. Some of the commonly used bus voltages are 28 V, 50 V, 72 V, 100 V, and 120 V. A DC/DC converter converts these voltages to secondary voltages such as 3.3 V, 5 V, 12 V, 15 V, and 28 V. Secondary bus voltages are further converted into usable voltages such as 0.8 V, 1.2 V, and 1.5 V with the help of points of load such as LDOs to feed to the microcontrollers (MCUs) and field-programable gate arrays (FPGAs) that drive the spacecraft loads.

A simplified power architecture for satellite applications, using Microchip’s standard rad-hard SA50-120 series of 50-W DC/DC power converters (Source: Microchip Technology Inc.) Environmental effects in space

The space environment consists of effects such as solar plasma, protons, electrons, galactic cosmic rays, and solar flare ions. This harsh environment causes environmental effects such as displacement damage, TID, and SEEs that result in device-level effects.

The power converter considerations should be in line with the orbits in which the satellite operates, as well as the mission time. For example, GEO has more stringent radiation requirements than LEO.

The volume requirement for LEO tends to be higher due to the number of smaller satellites launched to form the constellations. The satellites’ power management faces stringent requirements and needs to comply with various MIL standards to withstand the harsh environment. The power supplies used in these satellites also need to minimize size, weight, power, and cost (SWaP-C).

Microchip provides DC/DC space converters that are suitable for these applications with the standard rad-hard SA50 series for deep space or traditional space satellites in GEO/MEO and the standard radiation-tolerant LE50 series for LEO/New Space applications. Using standard components in a non-hybrid structure (die and wire bond with hermetically sealed construction) can prevent lot jeopardy and mission schedule risk to ensure reliable and rugged solutions with faster time to market at the desired cost.

In addition to the ruggedness and SWaP-C requirements, power supply solutions also need to be scalable to cover a wide range of quality levels within the same product series. This also includes offering a range of packaging materials and qualification options to meet mission goals.

For example, Microchip’s LE50-28 isolated DC/DC power converters are available in nine variants, with single and triple outputs for optimal design configurability. The power converters have a companion EMI filter and enable engineers to design to scale and customize by choosing one to three outputs based on the voltage range needed for the end application. This series provides flexibility with up to four power converters to reach 200 W. It offers space-grade radiation tolerance with 50-Krad TID and SEE latch-up immunity of 37-MeV·cm2/mg linear energy transfer.

The space-grade LE50-28 series is based on a forward topology that offers higher efficiency and <1% output ripple. It is housed in a compact package, measuring 3.055 × 2.055 × 0.55 inches with a low weight of just 120 grams. These standard non-hybrid, radiation-tolerant devices in a surface-mount package comply with MIL-STD-461, MIL-STD-883, and MIL-STD-202.

In addition, the LE50-28 DC/DC power converters, designed for 28-V bus systems, can be integrated with Microchip’s PolarFire FPGAs, MCUs, and LX7720-RT motor control sensors for a complete electrical system solution. This enables customers to use cost-effective, standard LE50 converters to customize and configure solutions using paralleling and synchronization features to form more intricate power systems that can meet the requirements of LEO power management.

For New Space’s low- to mid-volume satellite constellations with stringent cost and schedule requirements, sub-Qualified Manufacturers List (QML) versions in plastic packages are the optimal solutions that provide the radiation tolerance of QML (space-grade) components to enable lower screening requirements for lower cost and shorter lead times. LE50 companions in this category are RTG4 FPGA plastic versions and the PIC64 high-performance spaceflight computing (PIC64-HPSC) LEO variant.

The post Choosing power supply components for New Space appeared first on EDN.

Multifunction devices are great…as long as you can find uses for all (or at least some) of those additional functions that you end up paying for, that is.

All other factors being equal (or at least roughly comparable), I tend to gravitate toward multifunction devices instead of a suite of single-function widget alternatives. The versatile smartphone is one obvious example of this trend; while I still own a collection of both still and video cameras, for example, they mostly collect dust on my shelves while I instead regularly reach for the front and rear cameras built into my Google Pixel phones. And most folks have already bailed on standalone cameras (if they ever even had one in the first place) long ago.

Speaking of multi-function devices, as well as of cameras, for that matter, let’s take a look at today’s teardown victim, NEEWER’s Replacement Battery and Charger Set:

It comes in three variants, supporting (and bundled with two examples of) batteries for Canon (shown here), Nikon, and Sony cameras, with MSRPs ranging from $36.49 to $73.99. It’s not only a charger, over both USB-C and micro-USB input options (a USB-A to micro-USB adapter cable is included, too), but also acts as a travel storage case for those batteries as well as memory cards:

And assuming the batteries are already charged, you can use them not only to power your camera but also to recharge an external device, such as a smartphone, via the USB-A output. My only critique would be that the USB-C connector isn’t bidirectional, too, i.e., able to do double-duty as both a charging input and an external-powering output.

When life gives you damaged devices, make teardown patients

As part of Amazon’s most recent early-October Prime Big Deal Days promotion, the company marked down a portion of the inventory in its Resale (formerly Warehouse) section, containing “Quality pre-owned, used, and open box products” (their words, not mine, and in summary: where Amazon resells past customer returns). I’ve regularly mentioned it in the past as a source of widgets for both my ongoing use and in teardowns, the latter often the result of my receiving something that didn’t work or was otherwise not-as-advertised, and Amazon refunding me what I paid and telling me not to bother returning it. Resale-sourced acquisitions don’t always pan out, but they do often enough (and the savings are significant enough) that I keep coming back.

Take the NEEWER Replacement Battery and Charger Set for Canon LP-E6 batteries, for example. It was already marked down from $36.49 to $26.63 by virtue of its inclusion in the Resale section, and the Prime Big Deal Days promotion knocked off an additional 25%, dropping the per-unit price to $19.97. So, I bought all three units that were available for sale, since LP-E6 batteries are compatible not only with my two Canon EOS 5D Mark IV DSLRs and my first-generation Blackmagic Design Pocket Cinema 6K video camera but also, courtesy of their ubiquity (along with that of the Sony-originated L-series, i.e., NP-F battery form factor) useful as portable power options for field monitors, flash and constant illumination sources, and the like.

From past experience with Warehouse-now-Resale-sourced acquisitions, I expected the packaging to be less-than-pristine compared to a brand-new alternative, and reality matched the lowered expectations. Here are the front and back panels of the first two devices’ outer boxes, in the first image accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes, which you’ll also see in other photos in this piece:

Flip up the top, however, and the insides were a) complete and b) in cosmetically acceptable and fully functional shape. Here are the contents of the first box shown earlier, for example:

The aforementioned USB-A to micro-USB adapter cable:

One of the two included batteries:

The device outsides:

And finally, its insides:

The third time’s NOT the charm

The third device, on the other hand…when I saw the clear plastic bag that it came in, I knew I was in for trouble:

Removing the box from the bag only made matters visually, at least, worse:

And when I flipped open the top…yikes (I’d already taken out the LP-E6 batteries, which ended up looking and working fine, from the box when I snapped the following shots):

From a charging-and-powering standpoint, the device still worked fine, believe it or not. But the inability to securely attach the lid to the base rendered it of low value at best (there are always, of course, thick rubber bands as an alternative lid-securing scheme, but they’d still leave a gap).

So, I got in touch with Amazon, who gave me a full refund and told me to keep the device to do with as I wished. I relocated the batteries to my Blackmagic camera case. And then I added the battery charger to my teardown pile. On that note, by the way, I’ve intentionally waited until now to show you the packaging underside:

Case underside:

And one of the slips of literature:

This was the only one of the three devices I bought that had the same warning in all three places. If I didn’t know better, I’d think they’d foreseen what I later had planned for it!

Difficulty in diving in

Time to get inside:

As with my recent Amazon Smart Plug teardown, I had a heck of a time punching through the seemingly straightforward seam around the edges of the interior portion:

But finally, after some colorful language, along with collateral damage:

I wrenched my way inside, surmounting the seemingly ineffective glue above the PCB in the process. The design’s likely hardware modularity is perhaps obvious; the portion containing the battery bays is unique to a particular product proliferation, with the remainder common to all three variants.

Remove the three screws holding the PCB in place:

And it lifts right out:

That chunk out of one corner of the wire-wound inductor in the middle came courtesy of yours truly and his habit of blindly jabbing various tools inside the device during the ham-fisted disassembly process. The foam along the left edge precludes the underside LEDs (which you’ll see shortly) from shining upward, instead redirecting their outputs out the front.

IC conundrums

The large IC to the right of the foam strip, marked as follows:

0X895D45

is an enigma; my research of both the topside marked text (via traditional Google search) and the image (via Google Lens) was fruitless. I’m guessing that it’s the power management controller, handling both battery charging and output sequencing functions; more precise information from knowledgeable readers would be appreciated in the comments.

The two identical ICs along the top edge, in eight-lead SOP packages, were unfortunately no easier to ID. They’re marked as follows:

PSD (company logo) AKJG
PAP8801

And along the right edge is another IC, also in an eight-lead SOP but this time with the leads connected to the package’s long edges, and top-side stamped thusly:

SPT (company logo) SP1081F
25CT03

This last one I’m more confident of. It appears to be the SP1081F synchronous buck regulator from Chinese semiconductor supplier Wuxi Silicon Power Microelectronics. And intermingled with all these ICs are various surface-mounted passives and such.

For additional perspective, next are some side-view shots:

And, last but not least, here’s the PCB underside, revealing the four aforementioned LEDs, a smattering of test points, and not much else (unless you’re into traces, that is):

There you have it! As always, please share your insights in the comments.

—Brian Dipert is the Principal at Sierra Media and a former technical editor at EDN Magazine, where he still regularly contributes as a freelancer.

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The post A battery charger that does even more appeared first on EDN.

The wide adoption of artificial-intelligence models has led to a redesign of data center infrastructure. Traditional data centers are being replaced with AI factories, specifically designed to meet the computational capacity and power requirements required by today’s machine-learning and generative AI workloads.

Data centers traditionally relied on a microprocessor-centric (CPU) architecture to support cloud computing, data storage, and general-purpose compute needs. However, with the introduction of large language models and generative AI applications, this architecture can no longer keep pace with the growing demand for computational capacity, power density, and power delivery required by AI models.

AI factories, by contrast, are purpose-built for large-scale training, inference, and fine-tuning of machine-learning models. A single AI factory can integrate several thousand GPUs, reaching power consumption levels in the megawatt range. According to a report from the International Energy Agency, global data center electricity consumption is expected to double from about 415 TWh in 2024 to approximately 945 TWh by 2030, representing almost 3% of total global electricity consumption.

To meet this power demand, a simple data center upgrade would be insufficient. It is therefore necessary to introduce an architecture capable of delivering high efficiency and greater power density.

Following a trend already seen in the automotive sector, particularly in electric vehicles, Nvidia Corporation presented at Computex 2025 an 800-VDC power architecture designed to efficiently support the multi-megawatt power demand required by the compute racks of next-generation AI factories.

Power requirements of AI factories

The power profile of an AI factory differs significantly from that of a traditional data center. Because of the large number of GPUs employed, an AI factory’s architecture requires high power density, low latency, and broad bandwidth.

To maximize computational throughput, an increasing number of GPUs must be packed into ever-smaller spaces and interconnected using high-speed copper links. This inevitably leads to a sharp rise in per-rack power demand, increasing from just a few dozen kilowatts in traditional data centers to several hundred kilowatts in AI factories.

The ability to deliver such high current levels using traditional low-voltage rails, such as 12, 48, and 54 VDC, is both technically and economically impractical. Resistive power losses, as shown in the following formula, increase exponentially with rising current, leading to a significant reduction in efficiency and requiring the use of copper connections with extremely large cross-sectional areas.

Presistive loss = V × I = R × I2

To support high-speed connectivity among multiple GPUs, Nvidia developed the NVLink point-to-point interconnect system. Now in its fifth generation, NVLink enables thousands of GPUs to share memory and computing resources for training and inference tasks as if they were operating within a single address space.

A single Nvidia GPU based on the Blackwell architecture (Figure 1) supports up to 18 NVLink connections at 100 GB/s, for a total bandwidth of 1.8 TB/s, twice that of the previous generation and 14× higher than PCIe Gen5.

Figure 1: Blackwell-architecture GPUs integrate two reticle-limit GPU dies into a single unit, connected by a 10-TB/s chip-to-chip link. (Source: Nvidia Corporation) 800-VDC power architecture

Traditional data center power distribution typically uses multiple, cascading power conversion stages, including utility medium-voltage AC (MVAC), low-voltage AC (LVAC, typically 415/480 VAC), uninterruptible power supply, and power distribution units (PDUs). Within the IT rack, multiple power supply units (PSUs) execute an AC-to-DC conversion before final DC-to-DC conversions (e.g., 54 VDC to 12 VDC) on the compute tray itself.

This architecture is inefficient for three main reasons. First, each conversion stage introduces power losses that limit overall efficiency. Second, the low-voltage rails must carry high currents, requiring large copper busbars and connectors. Third, the management of three-phase AC power, including phase balancing and reactive power compensation, requires a complex design.

Conversely, the transition to an 800-VDC power backbone minimizes I2R resistive losses. By doubling the distribution voltage from the industry-standard high end (e.g., 400 VDC) to 800 VDC, the system can deliver the same power output while halving the current (P = V × I), reducing power loss by a factor of four for a given conductor resistance.

By adopting this solution, next-generation AI factories will have a centralized primary AC-to-DC conversion outside the IT data hall, capable of converting MVAC directly to a regulated 800-VDC bus voltage. This 800 VDC can then be distributed directly to the compute racks via a simpler, two-conductor DC busway (positive and return), eliminating the need for AC switchgear, LVAC PDUs, and the inefficient AC/DC PSUs within the rack.

Nvidia’s Kyber rack architecture is designed to leverage this simplified bus. Power conversion within the rack is reduced to a single-stage, high-ratio DC-to-DC conversion (800 VDC to the 12-VDC rail used by the GPU complex), often employing highly efficient LLC resonant converters. This late-stage conversion minimizes resistive losses, provides more space within the rack for compute, and improves thermal management.

This solution is also capable of scaling power delivery from the current 100-kW racks to over 1 MW per rack using the same infrastructure, ensuring that the AI factory’s power-delivery infrastructure can support future increased GPU energy requirements.

The 800-VDC architecture also mitigates the volatility of synchronous AI workloads, which are characterized by short-duration, high-power spikes. Supercapacitors located near the racks help attenuate sub-second peaks, while battery energy storage systems connected to the DC bus manage slower events (seconds to minutes), decoupling the AI factory’s power demand from the grid’s stability requirements.

The role of wide-bandgap semiconductors

The implementation of 800-VDC architecture can benefit from the superior performance and efficiency offered by wide-bandgap semiconductors such as silicon carbide and gallium nitride.

SiC MOSFETs are the preferred technology for the high-voltage front-end conversion stages (e.g., AC/DC conversion of 13.8-kV utility voltage to 800 VDC, or in solid-state transformers). SiC devices, typically rated for 1,200 V or higher, offer higher breakdown voltage and lower conduction losses compared with silicon at these voltage levels, despite operating at moderately high switching frequencies. Their maturity and robustness make them the best candidates for handling the primary power entry point into the data center.

GaN HEMTs, on the other hand, are suitable for high-density, high-frequency DC/DC conversion stages within the IT rack (e.g., 800 VDC to 54 VDC or 54 VDC to 12 VDC). GaN’s material properties, such as higher electron mobility, lower specific on-resistance, and reduced gate charge, enable switching frequencies into the megahertz range.

This high-frequency operation permits the use of smaller passive components (inductors and capacitors), reducing the size, weight, and volume of the converters. GaN-based converters have demonstrated power densities exceeding 4.2 kW/l, ensuring that the necessary power conversion stages can fit within the constrained physical space near the GPU load, maximizing the compute-to-power-delivery ratio.

Market readiness

Leading semiconductor companies, including component manufacturers, system integrators, and silicon providers, are actively collaborating with Nvidia to develop full portfolios of SiC, GaN, and specialized silicon components to support the supply chain for this 800-VDC transition.

For example, Efficient Power Conversion (EPC), a company specializing in advanced GaN-based solutions, has introduced the EPC91123 evaluation board, a compact, GaN-based 6-kW converter that supports the transition to 800-VDC power distribution in emerging AI data centers.

The converter (Figure 2) steps 800 VDC down to 12.5 VDC using an LLC topology in an input-series, output-parallel (ISOP) configuration. Its GaN design delivers high power density, occupying under 5,000 mm2 with a height of 8 mm, well-suited for tightly packed server boards. Placing the conversion stage close to the load reduces power losses and increases overall efficiency.

Figure 2: The EPC GaN converter evaluation board integrates the 150-V EPC2305 and the 40-V EPC2366 GaN FETs. (Source: Efficient Power Conversion)

Navitas Semiconductor, a semiconductor company offering both SiC and GaN devices, has also partnered with Nvidia to develop an 800-VDC architecture for the emerging Kyber rack platform. The system uses Navitas’s GaNFast, GaNSafe, and GeneSiC technologies to deliver efficient, scalable power tailored to heavy AI workloads.

Navitas introduced 100-V GaN FETs in dual-side-cooled packages designed for the lower-voltage DC/DC stages used on GPU power boards, along with a new line of 650-V GaN FETs and GaNSafe power ICs that integrate control, drive, sensing, and built-in protection functions. Completing the portfolio are GeneSiC devices, built on the company’s proprietary trench-assisted planar technology, that offer one of the industry’s widest voltage ranges—from 650 V to 6,500 V—and are already deployed in multiple megawatt-scale energy storage systems and grid-tied inverter projects.

Alpha and Omega Semiconductor Limited (AOS) also provides a portfolio of components (Figure 3) suitable for the demanding power conversion stages in an AI factory’s 800-VDC architecture. Among these are the Gen3 AOM020V120X3 and the top-side-cooled AOGT020V120X2Q SiC devices, both suited for use in power-sidecar configurations or in single-step systems that convert 13.8-kV AC grid input directly to 800 VDC at the data center’s edge.

Inside the racks, AOS supports high-density power delivery through its 650-V and 100-V GaN FET families, which efficiently step the 800-VDC bus down to the lower-voltage rails required by GPUs.

In addition, the company’s 80-V and 100-V stacked-die MOSFETs, along with its 100-V GaN FETs, are offered in a shared package footprint. This commonality gives designers flexibility to balance cost and efficiency in the secondary stage of LLC converters as well as in 54-V to 12-V bus architectures. AOS’s stacked-die packaging technology further boosts achievable power density within secondary-side LLC sockets.

Figure 3: AOS’s portfolio supports 800-VDC AI factories. (Source: Alpha and Omega Semiconductor Limited)

Other leading semiconductor companies also announced their readiness to support the transition to 800-VDC power architecture, including Renesas Electronics Corp. (GaN power devices) and Innoscience (GaN power devices), onsemi (SiC and silicon devices), Texas Instruments Inc. (GaN and silicon power modules and high-density power stages), and Infineon Technologies AG (GaN, SiC, and silicon power devices).

For example, Texas Instruments recently released a 30-kW reference design for powering AI servers. The design uses a two-stage architecture built around a three-phase, three-level flying-capacitor PFC converter, which is then followed by a pair of delta-delta three-phase LLC converters. Depending on system needs, the unit can be configured to deliver a unified 800-VDC output or split into multiple isolated outputs.

Infineon, besides offering its CoolSiC, CoolGaN, CoolMOS, and OptiMOS families of power devices, also introduced a 48-V smart eFuse family and a reference board for hot-swap controllers, designed for 400-V and 800-V power architectures in AI data centers. This enables developers to design a reliable, robust, and scalable solution to protect and monitor energy flow.

The reference design (Figure 4) centers on Infineon’s XDP hot-swap controller. Among high-voltage devices suitable for a DC bus, the 1,200-V CoolSiC JFET offers the right balance of low on-resistance and ruggedness for hot-swap operation. Combined with this SiC JFET technology, the digital controller can drive the device in linear mode, allowing the power system to remain safe and stable during overvoltage conditions. The reference board also lets designers program the inrush-current profile according to the device’s safety operating area, supporting a nominal thermal design power of 12 kW.

Figure 4: Infineon’s XDP hot-swap controller reference design supports 400-V/800-V data center architectures. (Source: Infineon Technologies AG)

The post The shift to 800-VDC power architectures in AI factories appeared first on EDN.

Delay lines are more than passive timing tricks—they are deliberate design elements that shape how signals align, synchronize, and stabilize across systems. From their theoretical roots in controlled propagation to their practical role in high-speed communication, test equipment, and signal conditioning, delay lines bridge abstract timing concepts with hands-on engineering solutions.

This article unpacks their principles, highlights key applications, and shows how understanding delay lines can sharpen both design insight and performance outcomes.

Delay lines: Fundamentals and classifications

Delay lines remain a fundamental building block in circuit design, offering engineers a straightforward means of controlling signal timing. From acoustic propagation experiments to precision imaging in optical coherence tomography, these elements underpin a wide spectrum of applications where accurate delay management is critical.

Although delay lines are ubiquitous, many engineers rarely encounter their underlying principles. At its core, a delay line is a device that shifts a signal in time, a deceptively simple function with wide-ranging utility. Depending on the application, this capability finds its way into countless systems. Broadly, delay lines fall into three physical categories—electrical, optical, and mechanical—and, from a signal-processing perspective, into two functional classes: analog and digital.

Analog delay lines (ADLs), often referred to as passive delay lines, are built from fundamental electrical components such as capacitors and inductors. They can process both analog and digital signals, and their passive nature allows attenuation between input and output terminals.

In contrast, digital delay lines (DDLs), commonly described as active delay lines, operate exclusively on digital signals. Constructed entirely from digital logic, they do not provide attenuation across terminals. Among DDL implementations, CMOS technology remains by far the most widely adopted logic family.

When classified by time control, delay lines fall into two categories: fixed and variable. Fixed delay lines provide a preset delay period determined by the manufacturer, which cannot be altered by the circuit designer. While generally less expensive, they are often less flexible in practical use.

Variable delay lines, by contrast, allow designers to adjust the magnitude of the delay. However, this tunability is bounded—the delay can only be varied within limits specified by the manufacturer, rather than across an unlimited range.

As a quick aside, bucket-brigade delay lines (BBDs) represent a distinctive form of analog delay. Implemented as a chain of capacitors clocked in sequence, they pass the signal step-by-step much like a line of workers handing buckets of water. The result is a time-shifted output whose delay depends on both the number of stages and the clock frequency.

While limited in bandwidth and prone to noise, BBDs became iconic in audio processing—powering classic chorus, flanger, and delay effects—and remain valued today for their warm, characterful sound despite the dominance of digital alternatives.

Other specialized forms of delay lines include acoustic devices (often ultrasonic), magnetostrictive implementations, surface acoustic wave (SAW) structures, and electromagnetic bandgap (EBG) delay lines. These advanced designs exploit material properties or engineered periodic structures to achieve controlled signal delay in niche applications ranging from ultrasonic sensing to microwave phased arrays.

There are more delay line types, but I deliberately omitted them here to keep the focus on the most widely used and practically relevant categories for designers.

Figure 1 The nostalgic MN3004 BBD showcases its classic package and vintage analog heritage. Source: Panasonic

Retro Note: Many grey-bearded veterans can recall the era when memory was not etched in silicon but rippled through wire. In magnetostrictive delay line memories, bits were stored as acoustic pulses traveling through nickel wire. A magnetic coil would twist the wire to launch a pulse—which propagated mechanically—and was sensed at the far end, then amplified and recirculated.

These memories were sequential, rhythmic, and beautifully analog, echoing the pulse logic of early radar and computing systems. Mercury delay line memories offered a similar acoustic storage medium in liquid form, prized for its stable acoustic properties. Though long obsolete, they remain a tactile reminder of a time when data moved not as electrons, but as vibrations.

And from my recollection of color television delay lines, a delay line keeps the faster, high-definition luminance signal (Y) in step with the slower, low-definition chrominance signal (C). Because the narrow-band chrominance requires more processing than the wide-band luminance, a brief but significant delay is introduced. The delay line compensates for this difference, ensuring that both signals begin scanning across the television screen in perfect synchrony.

Selecting the right delay line

It’s now time to focus on choosing a delay line that will function effectively in your circuit. To ensure compatibility with your electrical network, you should pay close attention to three key specifications. The first is line type, which determines whether you need a fixed or variable delay line and whether it must handle analog or digital signals.

The second is rise time, generally defined as the interval required for a signal’s magnitude to increase from 10% to 90% of its final amplitude. The third is time delay, the actual duration by which the delay line slows down the signal, expressed in units of time. Considering these parameters together will guide you toward a delay line that matches both the functional and performance requirements of your design.

Figure 2 A retouched snip from the legacy DS1021 datasheet shows its key specifications. Source: Analog Devices

Keep in mind that the DS1021 device, once a staple programmable delay line, is now obsolete. Comparable functionality is available on DS1023 or in modern timing ICs such as the LTC6994, which deliver finer programmability and ongoing support.

Digital-to-time converters: Modern descendants of delay lines

Digital-to-time converters (DTCs) represent the contemporary evolution of delay line concepts. Whereas early delay lines stored bits as acoustic pulses traveling through wire or mercury, a DTC instead maps a digital input word directly into a precise time delay or phase shift.

This enables designers to control timing edges with sub-nanosecond accuracy, a capability central to modern frequency synthesizers, clock generation, and high-speed signal processing. In effect, DTCs carry forward the spirit of delay lines—transforming digital code into controlled timing—but with the precision, programmability, and integration demanded by today’s systems.

Coming to practical points on DTC, unlike classic delay line ICs that were sold as standalone parts, DTCs are typically embedded within larger timing devices such as fractional-N PLLs, clock-generation ICs, or implemented in FPGAs and ASICs. Designers will not usually find a catalog chip labeled “DTC,” but they will encounter the function inside modern frequency synthesizers and RF transceivers.

This integration reflects the shift from discrete delay elements to highly integrated timing blocks, where DTCs deliver picosecond-level resolution, built-in calibration, and jitter control as part of a broader system-on-chip (SoC) solution.

Wrap-up: Delay lines for makers

For hobbyists and makers, the PT2399 IC has become a refreshing antidote to the fog of complexity.

Figure 3 PT2399’s block diagram illustrates internal functional blocks. Source: PTC

Originally designed as a digital echo processor, it integrates a simple delay line engine that can be coaxed into audio experiments without the steep learning curve of PLLs or custom DTC blocks. With just a handful of passive components, PT2399 lets enthusiasts explore echoes, reverbs, and time-domain tricks, inspiring them to get their hands dirty with audio and delay line projects.

In many ways, it democratizes the spirit of delay lines, bringing timing control out of the lab and into the workshop, where curiosity and soldering irons meet. And yes, I will add some complex design pointers in the seasoned landscape—but after some lines of delay.

Well, delay lines may have shifted from acoustic pulses to embedded timing blocks, but they still invite engineers to explore timing hands‑on.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Delay lines demystified: Theory into practice appeared first on EDN.

If the Consumer Electronics Show (CES) is a benchmark for what’s next in the electronic component industry, you’ll find that artificial intelligence permeates across all industries, from consumer electronics and wearables to automotive and robotics. Many chipmakers are placing big bets on edge AI as a key growth area along with robotics and IoT.

Here’s a sampling of the latest devices and technologies launched at CES 2026, covering AI advances for automotive, robotics, and wearables applications.

AI SoCs, chiplets, and development

Ambarella Inc. announced its CV7 edge AI vision system-on-chip (SoC), optimized for a wide range of AI perception applications, such as advanced AI-based 8K consumer products (action and 360° cameras), multi-imager enterprise security cameras, robotics (aerial drones), industrial automation, and high-performance video conferencing devices. The 4-nm SoC provides simultaneous multi-stream video and advanced on-device edge AI processing while consuming very low power.

The CV7 may also be used for multi-stream automotive designs, particularly for those running convolutional neural networks (CNNs) and transformer-based networks at the edge, such as AI vision gateways and hubs in fleet video telematics, 360° surround-view and video-recording applications, and passive advanced driver-assistance systems (ADAS).

Compared with its predecessor, the CV7 consumes 20% less power, thanks in part to Samsung’s 4-nm process technology, which is Ambarella’s first on this node, the company said. It incorporates Ambarella’s proprietary AI accelerator, image-signal processor (ISP), and video encoding, together with Arm cores, I/Os, and other functions for an efficient AI vision SoC.

The high AI performance is powered by Ambarella’s proprietary, third-generation CVflow AI accelerator, with more than 2.5× AI performance over the previous-generation CV5 SoC. This allows the CV7 to support a combination of CNNs and transformer networks, running in tandem.

In addition, the CV7 provides higher-performance ISP, including high dynamic range (HDR), dewarping for fisheye cameras, and 3D motion-compensated temporal filtering with better image quality than its predecessor, thanks to both traditional ISP techniques and AI enhancements. It provides high image quality in low light, down to 0.01 lux, as well as improved HDR for video and images.

Other upgrades include its hardware-accelerated video encoding (H.264, H.265, MJPEG), which boosts encode performance by 2× over the CV5 and its on-chip general-purpose processing upgrade to a quad-core Arm Cortex-A73, offering 2× higher CPU performance over the previous SoC. It also provides a 64-bit DRAM interface, delivering a significant improvement in available DRAM bandwidth compared with the CV5, Ambarella said. CV7 SoC samples are available now.

Ambiq Micro Inc. delivers the industry’s first ultra-low-power neural processing unit (NPU) built on its Subthreshold Power Optimized Technology (SPOT) platform. It is designed for real-time, always-on AI at the edge.

Delivering both performance and low power consumption, the SPOT-optimized NPU is claimed as the first to leverage sub- and near-threshold voltage operation for AI acceleration to deliver leading power efficiency for complex edge AI workloads. It leverages the Arm Ethos-U85 NPU, which supports sparsity and on-the-fly decompression, enabling compute-intensive workloads directly on-device, with 200 GOPS of on-device AI performance.

It also incorporates SPOT-based ultra-wide-range dynamic voltage and frequency scaling that enables operation at lower voltage and lower power than previously possible, Ambiq said, making room in the power budget for higher levels of intelligence.

Ambiq said the Atomiq SoC enables a new class of high-performance, battery-powered devices that were previously impractical due to power and thermal constraints. One example is smart cameras and security for always-on, high-resolution object recognition and tracking without frequent recharging or active cooling.

For development, Ambiq offers the Helia AI platform, together with its AI development kits and the modular neuralSPOT software development kit.

Ambiq’s Atomiq SoC (Source: Ambiq Micro Inc.)

On the development side, Cadence Design Systems Inc. and its IP partners are delivering pre-validated chiplets, targeting physical AI, data center, and high-performance computing (HPC) applications. Cadence announced at CES a partner ecosystem to deliver pre-validated chiplet solutions, based on the Cadence physical AI chiplet platform. Initial IP partners include Arm, Arteris, eMemory, M31 Technology, Silicon Creations, and Trilinear Technologies, as well as silicon analytics partner proteanTecs.

The new chiplet spec-to-packaged parts ecosystem is designed to reduce engineering complexity and accelerate time to market for developing chiplets. To help reduce risk, Cadence is also collaborating with Samsung Foundry to build out a silicon prototype demonstration of the Cadence physical AI chiplet platform. This includes pre-integrated partner IP on the Samsung Foundry SF5A process.

Extending its close collaboration with Arm, Cadence will use Arm’s advanced Zena Compute Subsystem and other essential IP for the physical AI chiplet platform and chiplet framework. The solutions will meet edge AI processing requirements for automobiles, robotics, and drones, as well as standards-based I/O and memory chiplets for data center, cloud, and HPC applications.

These chiplet architectures are standards-compliant for broad interoperability across the chiplet ecosystem, including the Arm Chiplet System Architecture and future OCP Foundational Chiplet System Architecture. Cadence’s Universal Chiplet Interconnect Express (UCIe) IP provides industry-standard die-to-die connectivity, with a protocol IP portfolio that enables fast integration of interfaces such as LPDDR6/5X, DDR5-MRDIMM, PCI Express 7.0, and HBM4.

Cadence’s physical AI chiplet platform (Source: Cadence Design Systems Inc.)

NXP Semiconductors N.V. launched its eIQ Agentic AI Framework at CES 2026, which simplifies agentic AI development and deployment for both expert and novice device makers. It is one of the first solutions to enable agentic AI development at the edge, according to the company. The framework works together with NXP’s secure edge AI hardware to help simplify agentic AI development and deployment for autonomous AI systems at the edge and eliminate development bottlenecks with deterministic real-time decision-making and multi-model coordination.

Offering low latency and built-in security, the eIQ Agentic AI Framework is designed for real-time, multi-model agentic workloads, including applications in robotics, industrial control, smart buildings, and transportation. A few examples cited include instantly controlling factory equipment to mitigate safety risks, alerting medical staff to urgent conditions, updating patient data in real time, and autonomously adjusting HVAC systems, without cloud connectivity.

For expert developers, they can integrate sophisticated, multi-agent workflows into existing toolchains, while novice developers can quickly build functional edge-native agentic systems without deep technical experience.

The framework integrates hardware-aware model preparation and automated tuning workflows. It enables developers to run multiple models in parallel, including vision, audio, time series, and control, while maintaining deterministic performance in constrained environments, NXP said. Workloads are distributed across CPU, NPU, and integrated accelerators using an intelligent scheduling engine.

The eIQ Agentic AI Framework supports the i.MX 8 and i.MX 9 families of application processors and Ara discrete NPUs. It aligns with open agentic standards, including Agent to Agent and Model Context Protocol.

NXP has also introduced its eIQ AI Hub, a cloud-based developer platform that gives users access to edge AI development tools for faster prototyping. Developers can deploy on cloud-connected hardware boards but still have the option for on-premise deployments.

NXP’s Agentic AI framework (Source: NXP Semiconductors N.V.) Sensing solutions

Bosch Sensortec launched its BMI5 motion sensor platform at CES 2026, targeting high-precision performance for a range of applications, including immersive XR systems, advanced robotics, and wearables. The new generation of inertial sensors—BMI560, BMI563, and BMI570—is built on the same hardware and is adapted through intelligent software.

Based on Bosch’s latest MEMS architecture, these inertial sensors, housed in an LGA package, claim ultra-low noise and exceptional vibration robustness. They offer twice the full-scale range of the previous generation. Key specifications include a latency of less than 0.5 ms, combined with a time increment of approximately 0.6 µs, and a timing resolution of 1 ns, which can deliver responsive motion tracking in highly dynamic environments.

The sensors also leverage a programmable edge AI classification engine that supports always-on functionality by analyzing motion patterns directly on the sensor. This reduces system power consumption and accelerates customer-specific use cases, the company said.

The BMI560, optimized for XR headsets and glasses, delivers low noise, low latency, and precise time synchronization. Its advanced OIS+ performance helps capture high-quality footage even in dynamic environments for smartphones and action cameras.

Targeting robotics and XR controllers, the BMI563 offers an extended full-scale range with the platform’s vibration robustness. It supports simultaneous localization and mapping, high dynamic XR motion tracking, and motion-based automatic scene tagging in action cameras.

The BMI570, optimized for wearables and hearables, delivers activity tracking, advanced gesture recognition, and accurate head-orientation data for spatial audio. Thanks to its robustness, it is suited for next-generation wearables and hearables.

Samples are now available for direct customers. High-volume production is expected to start in the third quarter of 2026.

Bosch also announced the BMI423 inertial measurement unit (IMU) at CES. The BMI423 IMU offers an extended measurement range of ±32 g (accelerometer) and ±4,000 dps (gyroscope), which enable precise tracking of fast, dynamic motion, making it suited for wearables, hearables, and robotics applications.

The BMI423 delivers low current consumption of 25 µA for always-on, acceleration-based applications in small devices. Other key specifications include low noise levels of 5.5 mdps/√Hz (gyro) and 90 µg/√Hz (≤ 8 g) or 120 µg/√Hz (≥ 16 g) (accelerometer), along with several interface options including I3C, I2C, and serial peripheral interface (SPI).

For wearables and hearables, the BMI423 integrates voice activity detection based on bone-conduction sensing, which helps save power while enhancing privacy, Bosch said. The sensor detects when a user is speaking and activates the microphone only when required. Other on-board functions include wrist-gesture recognition, multi-tap detection, and step counting, allowing the main processor to remain in sleep mode until needed and extending battery life in compact devices such as smartwatches, earbuds, and fitness bands.

The BMI423 is housed in a compact, 2.5 × 3 × 0.8-mm3 LGA package for space-constrained devices. The BMI423 will be available through Bosch Sensortec’s distribution partners starting in the third quarter of 2026.

Bosch Sensortec’s BMI563 IMU for robotics (Source: Bosch Sensortec)

Also targeting hearables and wearables, TDK Corp. launched a suite of InvenSense SmartMotion custom sensing solutions for true wireless stereo (TWS) earbuds, AI glasses, augmented-reality eyewear, smartwatches, fitness bands, and other IoT devices. The three newest IMUs are based on TDK’s latest ultra-low-power, high-performance ICM-456xx family that offers edge intelligence for consumer devices at the highest motion-tracking accuracy, according to the company.

Instead of relying on central processors, SmartMotion on-chip software enables computational processing related to motion tracking to be offloaded to the motion sensor itself so that intelligence decisions may be made locally, which allows other parts of the system to remain in low-power mode, TDK said. In addition, the sensor fusion algorithm and machine-learning capability are reported to deliver seamless motion sensing with minimum software effort by the customer.

The SmartMotion solutions, based on the ICM-456xx family of six-axis IMUs, include the SmartMotion ICM-45606 for TWS applications including earbuds, headphones, and other hearable products; the SmartMotion ICM-45687 for wearable and IoT technology; and the SmartMotion for Smart Glasses ICM-45685, which now enables new features, including sensing whether users are putting glasses on or taking glasses off (wear detection) and vocal vibration detection for identifying the source of the speech through its on-chip sensor fusion algorithms. The ICM-45685 also enables high-precision head-orientation tracking, optical/electronic image stabilization, intuitive UI control, posture recognition, and real-time translation.

TDK’s SmartMotion ICM-45685 (Source: TDK Corp.)

TDK also announced a new group company, TDK AIsight, to address technologies needed for AI glasses. The company will focus on the development of custom chips, cameras, and AI algorithms enabling end-to-end system solutions. This includes combining software technologies such as eye intent/tracking and multiple TDK technologies, such as sensors, batteries, and passive components.

As part of the launch, TDK AIsight introduced the SED0112 microprocessor for AI glasses. The next-generation, ultra-low-power digital-signal processor (DSP) platform integrates a microcontroller (MCU), state machine, and hardware CNN engine. The built-in hardware CNN architecture is optimized for eye intent. The MCU features ultra-low-power DSP processing, eyeGenI sensors, and connection to a host processor.

The SED0112, housed in a 4.6 × 4.6-mm package, supports the TDK AIsight eyeGI software and multiple vision sensors at different resolutions. Commercial samples are available now.

SDV devices and development

Infineon Technologies AG and Flex launched their Zone Controller Development Kit. The modular design for zone control units (ZCUs) is aimed at accelerating the development of software-defined-vehicle (SDV)-ready electrical/electronic architectures. Delivering a scalable solution, the development kit combines about 30 unique building blocks.

With the building block approach, developers can right-size their designs for different implementations while preserving feature headroom for future models, the company said. The design platform enables over 50 power distribution, 40 connectivity, and 10 load control channels for evaluation and early application development. A dual MCU plug-on module is available for high-end ZCU implementations that need high I/O density and computational power.

The development kit enables all essential zone control functions, including I2t (ampere-squared seconds), overcurrent protection, overvoltage protection, capacitive load switching, reverse-polarity protection, secure data routing with hardware accelerators, A/B swap for over-the-air software updates, and cybersecurity. The pre-validated hardware combines automotive semiconductor components from Infineon, including AURIX MCUs, OPTIREG power supply, PROFET and SPOC smart power switches, and MOTIX motor control solutions with Flex’s design, integration, and industrialization expertise. Pre-orders for the Zone Controller Development Kit are open now.

Infineon and Flex’s Zone Controller Development Kit (Source: Infineon Technologies AG)

Infineon also announced a deeper collaboration with HL Klemove to advance technologies in vehicle electronic architectures for SDVs and autonomous driving. This strategic partnership will leverage Infineon’s semiconductor and system expertise with HL Klemove’s capabilities in advanced autonomous-driving systems.

The three key areas of collaboration are ZCUs, vehicle Ethernet-based ADAS and camera solutions, and radar technologies.

The companies will jointly develop zone controller applications using Infineon’s MCUs and power semiconductors, with HL Klemove as the lead in application development. Enabling high-speed in-vehicle network solutions, the partnership will also develop front camera modules and ADAS parking control units, leveraging Infineon’s Ethernet technology, while HL Klemove handles system and product development.

Lastly, HL Klemove will use Infineon’s radar semiconductor solutions to develop high-resolution and short-range satellite radar. They will also develop high-resolution imaging radar for precise object recognition.

NXP introduced its S32N7 super-integration processor series, designed to centralize core vehicle functions, including propulsion, vehicle dynamics, body, gateway, and safety domains. Targeting SDVs, the S32N7 series, with access to core vehicle data and high compute performance, becomes the central AI control point.

Enabling scalable hardware and software across models and brands, the S32N7 simplifies vehicle architectures and reduces total cost of ownership by as much as 20%, according to NXP, by eliminating dozens of hardware modules and delivering enhanced efficiencies in wiring, electronics, and software.

NXP said that by centralizing intelligence, automakers can scale intelligent features, such as personalized driving, predictive maintenance, and virtual sensors. In addition, the high-performance data backbone on the S32N7 series provides a future-proof path for upgrading to the latest AI silicon without re-architecting the vehicle.

The S32N7 series, part of NXP’s S32 automotive processing platform, offers 32 compatible variants that provide application and real-time compute with high-performance networking, hardware isolation technology, AI, and data acceleration on an SoC. They also meet the strict timing, safety, and security requirements of the vehicle core.

Bosch announced that it is the first to deploy the S32N7 in its vehicle integration platform. NXP and Bosch have co-developed reference designs, safety frameworks, hardware integration, and an expert enablement program.

The S32N79, the superset of the series, is sampling now with customers.

NXP’s S32N7 super-integration processor series (Source: NXP Semiconductors N.V.)

Texas Instruments Inc. (TI) expanded its automotive portfolio for ADAS and SDVs with a range of automotive semiconductors and development resources for automotive safety and autonomy across vehicle models. The devices include the scalable TDA5 HPC SoC family, which offers power- and safety-optimized processing and edge AI; the single-chip AWR2188 8 × 8 4D imaging radar transceiver, designed to simplify high-resolution radar systems; and the DP83TD555J-Q1 10BASE-T1S Ethernet physical layer (PHY).

The TDA5 SoC family offers edge AI acceleration from 10 TOPS to 1,200 TOPS, with power efficiency beyond 24 TOPS/W. This scalability is enabled by its chiplet-ready design with UCIe interface technology, TI said, enabling designers to implement different feature sets.

The TDA5 SoCs provide up to 12× the AI computing of previous generations with similar power consumption, thanks to the integration of TI’s C7 NPU, eliminating the need for thermal solutions. This performance supports billions of parameters within language models and transformer networks, which increases in-vehicle intelligence while maintaining cross-domain functionality, the company said. It also features the latest Arm Cortex-A720AE cores, enabling the integration of more safety, security, and computing applications.

Supporting up to SAE Level 3 vehicle autonomy, the TDA5 SoCs target cross-domain fusion of ADAS, in-vehicle infotainment, and gateway systems within a single chip and help automakers meet ASIL-D safety standards without external components.

TI is partnering with Synopsys to provide a virtual development kit for TDA5 SoCs. The digital-twin capabilities help engineers accelerate time to market for their SDVs by up to 12 months, TI said.

The AWR2188 4D imaging radar transceiver integrates eight transmitters and eight receivers into a single launch-on-package chip for both satellite and edge architectures. This integration simplifies higher-resolution radar systems because 8 × 8 configurations do not require cascading, TI said, while scaling up to higher channel counts requires fewer devices.

The AWR2188 offers enhanced analog-to-digital converter data processing and a radar chirp signal slope engine, both supporting 30% faster performance than currently available solutions, according to the company. It supports advanced radar use cases such as detecting lost cargo, distinguishing between closely positioned vehicles, and identifying objects in HDR scenarios. The transceiver can detect objects with greater accuracy at distances greater than 350 meters.

With Ethernet an enabler of SDVs and higher levels of autonomy, the DP83TD555J-Q1 10BASE-T1S Ethernet SPI PHY with an integrated media access controller offers nanosecond time synchronization, as well as high reliability and Power over Data Line capabilities. This brings high-performance Ethernet to vehicle edge nodes and reduces cable design complexity and costs, TI said.

The TDA54 software development kit is now available on TI.com. Samples of the TDA54-Q1 SoC, the first device in the family, will be sampling to select automotive customers by the end of 2026. Pre-production quantities of the AWR2188 transceiver, AWR2188 evaluation module, DP83TD555J-Q1 10BASE-T1S Ethernet PHY, and evaluation module are now available on request at TI.com.

Robotics: processors and modules

Qualcomm Technologies Inc. introduced a next-generation robotics comprehensive-stack architecture that integrates hardware, software, and compound AI. As part of the launch, Qualcomm also introduced its latest, high-performance robotics processor, the Dragonwing IQ10 Series, for industrial autonomous mobile robots and advanced full-sized humanoids.

The Dragonwing industrial processor roadmap supports a range of general-purpose robotics form factors, including humanoid robots from Booster, VinMotion, and other global robotics providers. This architecture supports advanced-perception, motion planning with end-to-end AI models such as VLAs and VMAs. These features enable generalized manipulation capabilities and human-robot interaction.

Qualcomm’s general-purpose robotics architecture with the Dragonwing IQ10 combines heterogeneous edge computing, edge AI, mixed-criticality systems, software, machine-learning operations, and an AI data flywheel, along with a partner ecosystem and a suite of developer tools. This portfolio enables robots to reason and adapt to the spatial and temporal environments intelligently, Qualcomm said, and is optimized to scale across various form factors with industrial-grade reliability.

Qualcomm’s growing partner ecosystem for its robotics platforms includes Advantech, APLUX, AutoCore, Booster, Figure, Kuka Robotics, Robotec.ai, and VinMotion.

Qualcomm’s Dragonwing IQ10 industrial processor (Source: Qualcomm Technologies Inc.)

Quectel Wireless Solutions released its SH602HA-AP smart robotic computing module. Based on the D-Robotics Sunrise 5 (X5M) chip platform and with an integrated Ubuntu operating system, the module features up to 10 TOPS of brain-processing-unit computing power. The robotic computing modules target demanding robotic workloads, supporting advanced large-scale models such as Transformer, Bird’s-Eye View, and Occupancy.

The module works seamlessly with Quectel’s independent LTE Cat 1, LTE Cat 4, 5G, Wi-Fi 6, and GNSS modules, offering expanded connectivity options and a broader range of robotics use cases. These include smart displays, express lockers, electricity equipment, industrial control terminals, and smart home appliances.

The module, measuring 40.5 × 40.5 × 2.9 mm, operates over the –25°C to 85°C temperature range. It supplies a default memory of 4 GB plus 32 GB and numerous memory options. It supports data input and fusion processing for multiple sensors, including LiDAR, structured light, time-of-flight, and voice, meeting the AI and vision requirements in robotic applications.

The module supports 4k video at 60 fps with video encoding and decoding, binocular depth processing, AI and visual simultaneous localization and mapping, speech recognition, 3D point-cloud computing, and other mainstream robot perception algorithms. It provides Bluetooth, DSI, RGMII, USB 3.0, USB 2.0, SDIO, QSPI, seven UART, seven I2C, and two I2S interfaces.

The module integrates easily with additional Quectel modules, such as the KG200Z LoRa and the FCS950 Wi-Fi and Bluetooth module for more connectivity options.

Quectel’s SH602HA-AP smart robotic computing module (Source: Quectel Wireless Solutions)

The post CES 2026: AI, automotive, and robotics dominate appeared first on EDN.

An onboard charger converts power between the power grid and electric vehicles or hybrid electric vehicles. Traditional systems use two stages of power conversion: a boost converter to implement unity power factor, and an isolated DC/DC converter to charge the batteries with isolation. Obviously, these two stages require additional components that decrease power density and increase costs.

Matrix converters use a single stage of conversion without a boost inductor and bulky electrolytic capacitors. When using bidirectional gallium nitride (GaN) power switches, the converters further reduce component count and increase power density.

Comparing two-stage power converters with single-stage matrix converters

A two-stage power converter, as shown in Figure 1, requires a boost inductor (LB) and a DC-link electrolytic capacitor (CB), as well as four metal-oxide semiconductors (MOSFETs) for totem-pole power factor correction (PFC). 

Figure 1 Two-stage power converter diagram with LB, CB, and four MOSFETs for totem-pole PFC. Source: Texas Instruments

A single-stage matrix converter, as shown in Figure 2, does not require a boost inductor nor a DC-link capacitor but does require bidirectional switches (S11 and S12). Connecting common drains or common sources of two individual MOSFETs forms the bidirectional switches. Alternatively, when adopting bidirectional GaN devices in matrix converters, the number of switches decreases. Table 1 compares the two types of converters.

Figure 2 Single-stage matrix converter diagram that does not require LB or CB, but necessitates the use of two bidirectional switches: S11 and S12 . Source: Texas Instruments 

	Two-stage power converter (totem pole power factor correction plus DC/DC)	Single-stage matrix converter
Boost inductor	Yes	No
DC-link electrolytic capacitor	Yes	No
Fast unidirectional switches	10	4
Bidirectional switches	0	4
Slow switches	2	0
Electromagnetic interference filter	Smaller	Larger
Input/output ripple current	Smaller	Larger
Power density	Lower	Higher
Power efficiency	Lower	Higher
Control algorithm	Simple	Complicated

Table 1 A two-stage AC/DC and single-stage matrix converter comparison. Source: Texas Instruments

Single-stage matrix converter topologies

There are three major topologies applied to EV onboard charger applications.

Topology No. 1: The LLC topology

Figure 3 shows the inductor-inductor-capacitor (LLC) topology. The LLC converter regulates current or voltage by modulating switching frequencies. Lr and Cr form a resonant tank to shape the resonant current. Selecting the proper control algorithms will achieve a unity power factor.

With a three-phase AC input, the voltage ripple on the primary side is much smaller compared to a single-phase AC input. Therefore, the LLC topology is more suitable for three-phase applications. LLC converters operate at a higher frequency and realize a wider range of zero voltage switching (ZVS) than other topologies.

Figure 3 An LLC-based matrix converter with a three-phase AC input. Source: Texas Instruments

Topology No. 2: The DAB topology

Figure 4 shows a dual active bridge (DAB)-based matrix converter. The DAB topology can apply to a three-phase or single-phase AC input. Controlling the inductor current will realize unity power factor naturally. The goal of a control algorithm is to realize a wide ZVS range to reduce switching losses, reduce root-mean-square (RMS) current to reduce conduction losses, and achieve low current total harmonic distortion and unity power factor.

Triple-phase shift is necessary to achieve these goals, including primary-side internal phase shift, secondary-side internal phase shift, and external phase shift between the primary side and secondary side. Additionally, modulating the switching frequency will extend the ZVS range.

Figure 4 A DAB-based matrix converter with a single-phase AC input. Source: Texas Instruments

Topology No. 3: The SR-based topology

Figure 5 shows a series resonant (SR) matrix converter. The resonant tank formed by Lr and Cr shapes the transformer current to reduce turnoff current and turnoff losses. Meanwhile, the reactive power is reduced, as are conduction and switching losses. Compared to the LLC topology, the switching frequency of SR matrix converters is fixed, but higher than the resonant frequency.

Figure 5 An SR-based matrix converter with a single-phase AC input. Source: Texas Instruments

The control algorithm of single-stage matrix converters

In an LLC topology-based onboard charger with a three-phase AC input, switching frequency modulation regulates the charging current or voltage and uses space vector control based on grid polarity. The voltage ripple applied to the resonant tank is small. The resonant tank determines gain variations and affects the converter’s operation.

A DAB or SR DAB-based onboard charger usually adopts triple-phase shift (TPS) control to naturally achieve unity power factor, a wide ZVS range, and low RMS current. Optimizing switching frequencies further reduces both conduction and switching losses.

Figure 6 illustrates pulse width modulation (PWM) waveforms of TPS control of matrix converters for a half AC cycle (for example, Vac > 0). Figure 4 shows where PWMs connect to the power switches: d1 denotes the internal phase shift between PWM1A and PWM4A, d2 denotes the internal phase shift between PWM5A and PWM6A, and d3 denotes the external phase shift between the middle point of d1 and d2. PWM1B and PWM4B are gate drives for the second pair of bidirectional switches.

Figure 6 TPS PWM waveforms for a single-stage matrix converter for a half AC cycle. Source: Texas Instruments

Regardless of the topology selected, matrix converters require bidirectional switches, formed by connecting two GaN or silicon carbide (SiC) switches with a common drain or common source. Bidirectional GaN switches are emerging devices, integrating two GaN devices with common drains and providing bidirectional control with a single device.

Matrix converters

Matrix converters use single-stage power conversion to achieve a unity power factor and DC/DC power conversion. They provide two major advantages in onboard charger applications:

• High power density through the use of single-stage conversion, while eliminating large boost inductors and bulky DC-link electrolytic capacitors.
• High power efficiency through reduced switching and conduction losses, and a single power-conversion stage.

There are still many challenges to overcome to expand the use of single-stage matrix converters to other applications. High ripple current is a concern for batteries that require a low ripple charging current. Matrix converters are also more susceptible to surge conditions given the lack of DC-link capacitors. Overall, however, matrix converters are gaining popularity, especially with the emergence of wide-band-gap switches and advanced control algorithms.

Sean Xu currently works as a system engineer in Texas Instruments’ Power Design Services team to develop power solutions using advanced technologies for automotive applications. Previously, he was a system and application engineer working on digital control solutions for enterprise, data center, and telecom power. He earned a Ph.D. degree from North Dakota State University and a Master’s degree from Beijing University of Technology, respectively.

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The post Power Tips #149: Boosting EV charger efficiency and density with single-stage matrix converters appeared first on EDN.

An AI-enabled electronic components procurement tool claims to boost OEM productivity by leveraging a software platform that negotiates prices, tracks spending, and monitors savings in real time. It takes your bill-of-materials (BOM) and uploads it to the system while leveraging AI agents to discover form-fit-function compatible parts and more.

ChipHub, founded in 2023, is a components procurement tool that aims to optimize operations and savings for OEMs by addressing the supply chain issues at the system level.

Figure 1 A lack of control on component pricing, availability, and spending matrices makes the supply chain operations challenging. Source: ChipHub

A standard components procurement tool

Envision a procurement platform empowering OEMs to directly engage with suppliers, enhancing control over annual expenditures ranging from millions to billions of dollars. Such a platform streamlines interactions with suppliers, fostering efficient negotiations and monitoring of cost-saving metrics.

A tool that, at a very high level, enables OEMs to negotiate commercial terms directly with suppliers, all on the platform with no emails and spreadsheets. It can support millions of SKUs and thousands of suppliers with four fundamental procurement premises.

1. A scalable platform that facilitates supplier negotiations.
2. It offers risk reduction because the component supplier knows who the end customer is.
3. It employs generative AI to allow technical teams to evaluate devices or specs while extracting information from the datasheet and performing cross-part analysis.
4. It provides record-keeping features to monitor savings for procurement staff.

Enter ChipHub, an AI-driven procurement tool tailored for hardware OEMs. Its agentic system leverages Model Context Protocol (MCP) to enable collaboration between multiple AI agents and humans to deliver the information supply chain professionals need. Features like this help reform component sourcing by offering time and cost efficiencies irrespective of the OEM’s scale.

Next, ChipHub offers the unified marketplace framework (UMF), which helps procurement teams across diverse sectors such as data centers, computing, networking, storage, power, consumer goods, industrial, and automotive. Users can implement UMF in a single day and start monitoring their spending and savings in real time.

Figure 2 The procurement tool enables OEMs to negotiate commercial terms directly with component suppliers and do it right on the platform. Source: ChipHub

Users such as procurement managers use the platform to search specific parts, and the system conducts cross-part analysis to find compatible options, including real-time pricing and inventory data from various ecosystem partners. So, they don’t have to spend hours manually searching for data and building comparison matrices.

The platform uses a system of multiple AI agents, with human oversight, to navigate the supply chain and provide insights into part availability and sourcing options. “We don’t house any parts; we are just enabling supply-based management,” said Aftab Farooqi, founder and CEO of ChipHub.

Do I really know my supply chain? According to Farooqi, that’s the fundamental question for procurement managers. “If they don’t have control and visibility of their supply chain, they could be vulnerable,” he added. He also acknowledged that ChipHub isn’t a solution for all OEMs.

“They could keep doing things the way they are doing,” Farooqi said. “But they can still subscribe to this platform and have it as a validation tool.” For example, OEMs can cross-check the signal integrity analysis of a particular component.

Farooqi added that the platform can also be used by contract manufacturers (CMs) as a key tool for risk reduction because it enables spend tracking and collaboration features on the platform.

Related Content

• Three steps to better procurement
• Software tools manage selection of components
• Semiconductor Supply Chain: The Role of Lean & Muda
• E-Commerce Is the Future of Components Procurement
• Europe’s Semiconductor Supply Chain Unleashes the Power of Diamond

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Microchip Technology has expanded its PolarFire FPGA–based smart embedded video ecosystem to enable low-power, high-bandwidth video connectivity. The offering consists of integrated development stacks that combine hardware evaluation kits, development tools, IP cores, and reference designs to deliver complete video pipelines for medical, industrial, and robotic vision applications. The latest additions include Serial Digital Interface (SDI) receive and transmit IP cores and a quad CoaXPress (CXP) bridge kit.

The ecosystem supports SMPTE-compliant SDI video transport at 1.5G, 3G, 6G, and 12G, along with HDMI-to-SDI and SDI-to-HDMI bridging for 4K and 8K video formats. PolarFire FPGAs enable direct SLVS-EC (up to 5 Gbps per lane) and CoaXPress 2.0 (up to 12.5 Gbps per lane) bridging without third-party IP. The nonvolatile, low-power architecture supports compact, fanless system designs with integrated hardware-based security features.

Native support for Sony SLVS-EC sensors provides an upgrade path for designs impacted by component discontinuations. Development is supported through Microchip’s Libero Design Suite and SmartHLS tools to simplify design workflows and reduce development time.

The following links provide additional information on PolarFire smart embedded vision, the CoaXPress bridge kit, and FPGA solution stacks.

Microchip Technology 

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Infineon’s EZ-USB FX2G3 USB 2.0 peripheral controllers provide DMA data transfers from LVCMOS inputs to USB outputs at speeds of up to 480 Mbps. Designed for USB Hi-Speed host systems, the devices also support Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) operation.

Built on the company’s MXS40-LP platform, EZ-USB FX2G3 controllers integrate up to six serial communication blocks (SCBs), a crypto accelerator supporting AES, DES, SHA, and RSA algorithms for enhanced security, and a high-bandwidth data subsystem with up to 1024 KB of SRAM for USB data buffering. Additional on-chip memory includes up to 512 KB of flash, 128 KB of SRAM, and 128 KB of ROM.

The family includes four variants, ranging from basic to advanced, all featuring a 100-MHz Arm Cortex-M0+ CPU, while the top-end device adds a 150-MHz Cortex-M4F. The peripheral I/O subsystem accommodates QSPI configurable in single, dual, quad, dual-quad, and octal modes. SCBs can be configured as I2C, UART, or SPI interfaces. The devices provide up to 32 configurable USB endpoints, making them suitable for a wide range of consumer, industrial, and healthcare applications.

EZ-USB FX2G3 controllers are now available in 104-pin, 8×8-mm LGA packages.

EZ-USB FX2G3 product page

Infineon Technologies  

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Diodes’ API772x RobustISO series of dual-channel digital isolators protects sensitive components in high-voltage systems. The devices provide reliable, robust isolation for digital control and communication signals in industrial automation, power systems, and data center power supplies.

Comprising six variants, the API772x series meets reinforced and basic isolation requirements across various standards, including VDE, UL, and CQC. The parts have a 5-kVRMS isolation rating for 1 minute per UL 1577 and an 8-kVPK rating per DIN EN IEC 60747-17 (VDE 0884-17). Maximum surge isolation voltage is 12.8 kVPK. According to Diodes’ isolation reliability calculations, the devices achieve a predicted operational lifetime exceeding 40 years, based on a capacitive isolation barrier more than 25 µm thick.

RobustISO digital isolators support a range of transmission protocols at data rates up to 100 Mbps. They feature a minimum common-mode transient immunity of 150 kV/µs, ensuring reliable signal transmission in noisy environments. Operating from a 2.5-V to 5.5-V supply, the devices typically draw 2.1 mA per channel at 100 Mbps. The series offers flexible digital channel-direction configurations and default output levels to accommodate diverse design requirements.

Prices for the API772x devices start at $0.46 each in lots of 1000 units.

RobustISO API772x product page

Diodes

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A 100-V, 200-A MOSFET from Rohm, the RS7P200BM achieves a wide safe operating area (SOA) in a compact DFN5060-8S (5×6-mm) package. The device safely handles inrush current and overload conditions, ensuring stable operation in hot-swap circuits for AI servers using 48-V power supplies.

The RS7P200BM features RDS(on) of 4.0 mΩ (VGS = 10 V, Ta = 25 °C) while maintaining a wide SOA—7.5 A for a 10‑ms pulse width and 25 A for 1 ms at VDS = 48 V. This combination of low on-resistance and wide SOA, typically a trade-off, helps suppress heat generation. As a result, server power supply efficiency improves, while cooling requirements and overall electricity costs are reduced.

Housed in a DFN5060-8S package, the RS7P200BM enables higher-density mounting than the previous DFN8080-8S design. It is now available in production quantities through online distributors including DigiKey and Mouser.

RS7P200BM product page 

Rohm Semiconductor 

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The Tronics AXO315T1 MEMS accelerometer from TDK is designed for oil and gas downhole navigation in extreme environments. It features a ±14‑g input range and a 24‑bit digital SPI interface for measurement-while-drilling (MWD) applications exposed to temperatures up to 175°C.

Powered by a unique closed-loop architecture, this single-axis device achieves a tenfold improvement in vibration rejection compared with conventional open-loop MEMS accelerometers. It offers vibration rejection of 20 µg/g², noise density of 10 µg/√Hz, and a bias residual error of 1.7 mg over a temperature range of –30 °C to +175 °C.

The AXO315T1 provides a cost-effective, digital, and low-SWaP alternative to quartz accelerometers for inclination measurement in directional drilling tools. It is rated for more than 1000 hours of operation at 175°C and is housed in a hermetically sealed, ceramic surface-mount package.

AXO315T1 sensors and evaluation boards are available for sampling and customer trials.

AXO315T1 product page

TDK Tronics 

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How does a wiggling groove on a rotating record transform into two-channel sonic excellence? It all starts with the turntable cartridge, mated to one of several possible needle types.

Mid-last year, I confessed that I’d headed back down the analog “vinyl” record rabbit hole after several decades of sole dedication to various digital audio media sources (physical, download and streamed). All three turntables now in my possession employ moving magnet cartridge technology; here’s what I wrote back in July in comparing it against the moving coil alternative:

Two main cartridge options exist: moving magnet and higher-end moving coil. They work similarly, at least in concept: in conjunction with the paired stylus, they transform physical info encoded onto a record via groove variations into electrical signals for eventual reproduction over headphones or a set of speakers. Differences between the two types reflect construction sequence variance of the cartridge’s two primary subsystems—the magnets and coils—and are reflected (additionally influenced by other factors such as cantilever constituent material and design) not only in perceived output quality but also in other cartridge characteristics such as output signal strength and ruggedness.

Miny-but-mighty magnets

And here’s more on moving magnet cartridges from Audio-Technica’s website:

Audio-Technica brand moving magnet-type cartridges carry a pair of small, permanent magnets on their stylus assembly’s cantilever. The cantilever is the tiny suspended “arm” that extends at an angle away from the cartridge body. The cantilever holds the diamond tip that traces the record groove on one end and transfers the vibrations from the tip to the other end where the magnets are located. These tiny magnets are positioned between two sets of fixed coils of wire located inside the cartridge body via pole pieces that extend outward from the coils. This arrangement forms the electromagnetic generator.

The magnets are the heaviest part of the moving assembly, but by mounting the magnets near the fulcrum, or pivot point, of the assembly the amount of mass the stylus is required to move is minimized, allowing it to respond quickly and accurately to the motion created by the record groove. In addition to enhancing response, the low effective tip mass reduces the force applied to the delicate record groove, reducing the possibility of groove wall wear and damage. The moving magnet-type cartridge produces moderate to high output levels, works easily into standard phono inputs on a stereo amplifier or receiver and has a user-replaceable stylus assembly. These cartridges have a robust design, making them an excellent choice for demanding applications such as live DJ, radio broadcasts and archiving.

The associated photo is unfortunately low-res and otherwise blurry:

Here’s a larger, clearer one, which I’d found within a tutorial published by retailer Crutchfield:

Inexpensively assuaging curiosity

Ever since I started dabbling with vinyl again, I’d been curious to take a moving magnet cartridge apart and see what was inside. I got my chance when I found a brand new one, complete with a conical stylus, on sale for $18.04 on eBay. It’s the AT3600L, the standalone version of the cartridge that comes pre-integrated with my Audio-Technica AT-LP60XBT turntable’s tonearm:

Here are some “stock” images of the AT3600L mated to the standard ATN3600LC conical stylus (with the protective plastic sleeve still over the needle):

This next set of shots accompanied the eBay post which had caught my eye (and wallet):

And, last but not least, here are some snaps of our dissection patient, first bagged as initially received:

then unbagged but still encased, and as usual (as well as with photos that follow) accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

along with mounting hardware at the bottom:

and finally, free from plastic captivity:

Conical closups and elliptical unpredictability

Next, let’s pop off the stylus and take a gander at its conical needle tip:

along with the cantilever and pivot assembly:

If you’ve already read my July coverage, you know that I’d also picked up an easily swappable:

elliptical stylus, the Pfanstiehl 4211-DE, which promised enhanced sonic quality:

but ended up being notably less tolerant than its conical sibling of any groove defects. Some of this functional variance, I noted back in July, is inherent to the needles’ structural deviations:

Because conical styli only ride partway down in the record groove, they supposedly don’t capture all the available fidelity potential with pristine records. But that same characteristic turns out to be a good thing with non-pristine records, for which all manner of gunk has accumulated over time in the bottom of the groove. By riding above the dross, the conical needle head doesn’t suffer from its deleterious effects.

But, as it turns out, the Pfanstiehl 4211-DE itself was also partly to “blame”. It reportedly works best with turntables based on the standalone AT3600L cartridge, whose tracking force and antiskating settings are both user-adjustable and lighter than those needed (non-adjustable, as well) with the fully integrated AT-LP60XBT turntable.

I resold the barely used Pfanstiehl 4211-DE on eBay and went with Audio-Technica’s (modestly) more pricey ATN3600LE elliptical stylus instead, which explicitly documented its compatibility with the AT-LP60 turntable series and indeed worked notably better with my setup:

Back to the ATN3600LC conical stylus. Two interior views showcase the magnets called out in the earlier concept image:

And here’s where they mate with the cartridge itself (with associated coils presumably inside, to be seen shortly):

Cartridge dissection

Next, let’s remove the screw that holds the top black plastic mounting assembly in place:

One more look at the connections at the back, with markings now visible:

And now, let’s peel away the metal casing, focusing attention on the top-side seam:

With that, the insides come right out:

That was a fun and informative, not to mention inexpensive, project that satisfied my curiosity. I hope it did the same for you. Sounds off with your thoughts in the comments, please!

—Brian Dipert is the Principal at Sierra Media and a former technical editor at EDN Magazine, where he still regularly contributes as a freelancer.

Related Content

• Hardware alterations: Unintended, apparent advantageous adaptations
• Mega-cool USB-based turntable
• Assessing vinyl’s resurrection: Differentiation, optimization, and demand maximization

The post Peeking inside a moving magnet phono cartridge and stylii appeared first on EDN.

Various designs for current mirror circuits have been an active topic recently here in Design Ideas (DIs). Usually, the mirror designer’s aim is to make the mirror’s input and output currents accurately equal, but Figure 1 shows one that takes a tangent. Being immune to traditional current mirror bugaboos (Early effect, etc.), it can achieve the equality criterion quite well, but it also has particular versatility in applications where the input and output currents deliberately differ.

Figure 1 The R1/R2 resistance ratio sets the I2/I1 current ratio.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Here’s the backstory: Awhile back, I published a DI that used the venerable family of TLx431 shunt voltage regulators as programmable current regulators: “Precision programmable current sink.”

Figure 1 demonstrates their versatility again, this time combining two of the beasties to make a programmable gain current mirror. 

The choice between the 2.5-V reference voltage TL431 and the 1.24-V TLV431 can be based on their different current and voltage ratings. For current: 1 mA to 100 mA for the TL versus 100 µA to 15 mA for the TLV. For voltage: 2.5 V to 36 V for the TL versus 1.24 V to 6 V for the TLV.

Note that both I1 and I2 must fall within those respective current numbers for useful regulation (and reflection!) to occur. Minimum mirror input voltage = Vref + I2R2.

Of course, you must also accommodate the modest heat dissipation limits of these small devices. However, the maximum current (and power) capabilities can be extended virtually without limit by the simple ploy shown in Figure 2.

Figure 2 Booster transistor Q1 can handle current and power beyond 431 max Ic and dissipation limits.

And one more thing. 

You might reasonably accuse Z1 of basically loafing since its only job is to provide bias voltage for R1 and Z2. But we can give it more interesting work to do with the trick shown in Figure 3. Not only can this scheme accommodate arbitrary I1/I2 ratios, but we can also add a fixed offset current! Here’s how.

Figure 3 Add six resistors and one transistor to two TL431s to make this 0/20 mA to 4/20 mA current loop converter. Z2 sums the 500-mV offset provided by Z1 with the 0 to 2 V made by current sensor R1, then scales that with R2 to output the 4 to 20 mA with a boost from Q1 that can accommodate loop voltages up to 36 V. Note R1, R2, R4, and R6 need to be precision types.

What results here is a (somewhat simpler) solution to an application borrowed from a previous DI by frequent contributor R Jayapal in: “A 0-20mA source current to 4-20mA loop current converter.”

In electronic design, it seems there’s always more than one way to defrock a feline.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Precision programmable current sink
• A 0-20mA source current to 4-20mA loop current converter
• Silly simple precision 0/20mA to 4/20mA converter

The post Combine two TL431 regulators to make versatile current mirror appeared first on EDN.

As high-performance computing (HPC) workloads become increasingly complex, generative artificial intelligence (AI) is being progressively integrated into modern systems, thereby driving the demand for advanced memory solutions. To meet these evolving requirements, the industry is developing next-generation memory architectures that maximize bandwidth, minimize latency, and enhance power efficiency.

Technology advances in DRAM, LPDDR, and specialized memory solutions are redefining computing performance, with AI-optimized memory playing a pivotal role in driving efficiency and scalability. This article examines the latest breakthroughs in memory technology and the growing impact of AI applications on memory designs.

Advanced memory architectures

Memory technology is advancing to meet the stringent performance requirements of AI, AIoT, and 5G systems. The industry is witnessing a paradigm shift with the widespread adoption of DDR5 and HBM3E, offering higher bandwidth and improved energy efficiency.

DDR5, with a per-pin data rate of up to 6.4 Gbps, delivers 51.2 GB/s per module, nearly doubling DDR4’s performance while reducing the voltage from 1.2 V to 1.1 V for improved power efficiency. HBM3E extends bandwidth scaling, exceeding 1.2 TB/s per stack, making it a compelling solution for data-intensive AI training models. However, it’s impractical for mobile and edge deployments due to excessive power requirements.

Figure 1 The above diagram chronicles memory scaling from MCU-based embedded systems to AI accelerators serving high-end applications. Source: Winbond

With LPDDR6 projected to exceed 150 GB/s by 2026, low-power DRAM is evolving toward higher throughput and energy efficiency, addressing the challenges of AI smartphones and embedded AI accelerators. Winbond is actively developing small-capacity DDR5 and LPDDR4 solutions optimized for power-sensitive applications around its CUBE memory platform, which achieves over 1 TB/s bandwidth with a significant reduction in thermal dissipation.

With anticipated capacity scaling up to 8 GB per set or even higher, such as 4Hi WoW, based on one reticle size, which can achieve >70 GB density and bandwidth of 40TB/s, CUBE is positioned as a viable alternative to traditional DRAM architectures for AI-driven edge computing.

In addition, the CUBE sub-series, known as CUBE-Lite, offers bandwidth ranging from 8 to 16 GB/s (equivalent to LPDDR4x x16/x32), while operating at only 30% of the power consumption of LPDDR4x. Without requiring an LPDDR4 PHY, system-on-chips (SoCs) only need to integrate the CUBE-Lite controller to achieve bandwidth performance comparable to full-speed LPDDR4x. This not only eliminates the high cost of PHY licensing but also allows the use of mature process nodes such as 28 nm or even 40 nm, achieving performance levels of 12-nm node.

This architecture is particularly suitable for AI SoCs or AI MCUs that come integrated with NPUs, enabling battery-powered TinyML edge devices. Combined with Micro Linux operating systems and AI model execution, it can be applied to low-power AI image sensor processor (ISP) edge scenarios such as IP cameras, AI glasses, and wearable devices, effectively achieving both system power optimization and chip area reduction.

Furthermore, SoCs without LPDDR4 PHY and only CUBE-light controller can achieve smaller die sizes and improved system power efficiency.

The architecture is highly suitable for AI SoCs—MCUs, MPUs, and NPUs—and TinyML endpoint AI devices designed for battery operation. The operating system is Micro Linux combined with an AI model for AI SoCs. The end applications include AI ISP for IP cameras, AI glasses, and wearable devices.

Figure 2 The above diagram chronicles the evolution of memory bandwidth with DRAM power usage. Source: Winbond

Memory bottlenecks in generative AI deployment

The exponential growth of generative AI models has created unprecedented constraints on memory bandwidth and latency. AI workloads, particularly those relying on transformer-based architectures, require extensive computational throughput and high-speed data retrieval.

For instance, deploying LLamA2 7B in INT8 mode requires at least 7 GB of DRAM or 3.5 GB in INT4 mode, which highlights the limitations of conventional mobile memory capacities. Current AI smartphones utilizing LPDDR5 (68 GB/s bandwidth) face significant bottlenecks, necessitating a transition to LPDDR6. However, interim solutions are required to bridge the bandwidth gap until LPDDR6 commercialization.

At the system level, AI edge applications in robotics, autonomous vehicles, and smart sensors impose additional constraints on power efficiency and heat dissipation. While JEDEC standards continue to evolve toward DDR6 and HBM4 to improve bandwidth utilization, custom memory architectures provide scalable, high-performance alternatives that align with AI SoC requirements.

Thermal management and energy efficiency constraints

Deploying large-scale AI models on end devices introduces significant thermal management and energy efficiency challenges. AI-driven workloads inherently consume substantial power, generating excessive heat that can degrade system stability and performance.

• On-device memory expansion: Mobile devices must integrate higher-capacity memory solutions to minimize reliance on cloud-based AI processing and reduce latency. Traditional DRAM scaling is approaching physical limits, necessitating hybrid architectures integrating high-bandwidth and low-power memory.
• HBM3E vs CUBE for AI SoCs: While HBM3E achieves high throughput, its power requirements exceed 30 W per stack, making it unsuitable for mobile and edge applications. Here, memory solutions like CUBE can serve as an alternative last level cache (LLC), reducing on-chip SRAM dependency while maintaining high-speed data access. The shift toward sub-7-nm logic processes exacerbates SRAM scaling limitations, emphasizing the need for new cache solutions.
• Thermal optimization strategies: As AI processing generates heat loads exceeding 15 W per chip, effective power distribution and dissipation mechanisms are critical. Custom DRAM solutions that optimize refresh cycles and employ TSV-based packaging techniques contribute to power-efficient AI execution in compact form factors.

DDR5 and DDR6: Accelerating AI compute performance

The evolution of DDR5 and DDR6 represents a significant inflexion point in AI system architecture, delivering enhanced memory bandwidth, lower latency, and greater scalability.

DDR5, with 8-bank group architecture and on-die error correction code (ECC), provides superior data integrity and efficiency, making it well-suited for AI-enhanced PCs and high-performance laptops. With an effective peak transfer rate of 51.2 GB/s per module, DDR5 enables real-time AI inference, seamless multitasking, and high-speed data processing.

DDR6, still in development, is expected to introduce bandwidth exceeding 200 GB/s per module, a 20% reduction in power consumption along with optimized AI accelerator support, further pushing AI compute capabilities to new limits.

Figure 3 CUBE, an AI-optimized memory solution, leverages through-silicon via (TSV) interconnects to integrate high-bandwidth memory characteristics with a low-power profile. Source: Winbond

The convergence of AI-driven workloads, performance scaling constraints, and the need for power-efficient memory solutions is shaping the transformation of the memory market. Generative AI continues to accelerate the demand for low-latency, high-bandwidth memory architectures, leading to innovation across DRAM and custom memory solutions.

As AI models become increasingly complex, the need for optimized, power-efficient memory architectures will become increasingly critical. Here, technological innovation will ensure commercial realization of cutting edge of AI memory solutions, bridging the gap between high-performance computing and sustainable, scalable memory devices.

Jacky Tseng is deputy director of CMS CUBE product line at Winbond. Prior to joining Winbond in 2011, he served as a senior engineer at Hon-Hai.

Special Section: AI Design

• The AI design world in 2026: What you need to know
• AI workloads demand smarter SoC interconnect design
• AI’s insatiable appetite for memory

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