Microelectronics world news

The Microchip PIC32-BZ6 family of wireless MCUs enables multiprotocol product development with advanced connectivity and scalability. These highly integrated devices support Bluetooth Low Energy, Thread, Matter, and proprietary protocols for smart home, automotive, industrial automation, and wireless motor control applications.

Replacing multichip solutions, the single-chip PIC32-BZ6 platform combines wired and wireless connectivity with a range of peripherals and ample memory. Analog peripherals support motor control, while touch and graphics capabilities enable rich user interfaces.

Qualified to Bluetooth Core Specification 6.0, the MCUs also support 802.15.4-based protocols and proprietary mesh networking. Interfaces for wired connectivity include two CAN-FD ports, a 10/100-Mbps Ethernet MAC, and a USB 2.0 full-speed transceiver.

PIC32-BZ6 MCUs are powered by a 128‑MHz Arm Cortex-M4Fcore and offer 2 MB of flash and 512 KB of RAM. A capacitive voltage divider supports up to 18 touch channels, while 12‑bit ADCs, 7‑bit DAC, comparators, PWMs, and QEI simplify motor control.

The PIC32-BZ6 platform currently includes a SoC and an RF-certified module, priced at $3.73 and $5.84 each, respectively, in quantities of 10,000 units.

PIC32-BZ6 product page 

Microchip Technology 

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Fitted with MEMS switches, two fault insertion units (FIUs) from Pickering simulate common faults in MultiGBASE-T1 communication links. The single-slot 40-205 (PXI) and 42-205 (PXIe) modules target automotive hardware-in-the-loop simulation, enabling design verification of networking components such as ADAS controllers at data rates up to 10 Gbps.

Both PXI and PXIe modules provide 4 or 8 channels of impedance-matched, two-wire signal paths that support communication protocols from legacy 10BASE-T1 to the 10GBASE-T1 automotive Ethernet standard. The FIUs help verify safe and consistent controller operation under a range of connectivity faults, including open and short circuits.

Leveraging MEMS technology, the signal channels deliver low insertion loss and VSWR, along with stable RF performance beyond 6 GHz. Fast 50-µs switching boosts test throughput, while the 3-billion-cycle lifetime ensures durability. Each channel handles up to 0.5 A and 100 V between wire pairs, and the 1.6-A fault buses allow multiple channels to share the same fault condition.

The 8-channel 40-205 (PXI) and 42-205 (PXIe) FIU modules are priced at $10,995 each.

40/42-205 product page 

Pickering Interfaces 

The post MEMS tech speeds automotive Ethernet fault tests appeared first on EDN.

Ascent Solar Technologies Inc of Thornton, CO, USA – which designs and makes lightweight, flexible copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) modules that can be integrated into consumer products, off-grid applications and aerospace applications – has delivered test samples of its thin-film PV technology to both an ocean monitoring technology company (a developer of autonomous underwater vehicles capable of reaching anywhere in the ocean with a high degree of speed, endurance and sensing) and a space power lasing company (focused on advancing space and defense technologies). ..

Recently, we’ve seen Design Ideas for programmable current sources with improved accuracy using the LM3x7 series of three-legged regulators. These designs also take advantage of those classic devices’ built-in anti-overheating features. 

Some are very good, like “Improve the accuracy of programmable LM317 and LM337-based power sources.”

Others perhaps not so much…“Cross-connect complementary current sources to reduce self-heating error”…

All of them, however, had to accommodate the LM3x7 family’s need for about 5-V of supply voltage headroom when used this way. That is the voltage drawn from the supply that can never be delivered to the load. It therefore creates significant inefficiency in power utilization. It might have been picky of me, but I couldn’t resist wondering what could be done to improve (reduce) the loss.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Current source without overtemperature protection

Figure 1 shows what I started with: A simple, straightforward, accurate, 0 to 1 A current source programmed with 0 to 2.5 V. It needs only about 1.25 V of headroom, consisting mostly of the drop of current sense resistor R1 (plus a modicum more from the Ron of Q1), thus fixing the problem I started out to solve.

Figure 1 An improved efficiency precision current source has no overtemperature protection. With no protection, if the Q1 heatsink is inadequate, high power or ambient temperature might destroy it.

But sadly, in fixing one problem, I created another. 

The same elimination of LM3x7s that reduced the headroom requirement also eliminated overtemperature protection. Without a substantial external heatsink, the Si7489DP FET is rated for only ~6 W at 25 °C. If power dissipation, ambient temperature, or both happen to go higher, there’s now nothing to prevent Q1 from being cooked.

Current source with overtemperature protection

So now I wondered what might be done about that. Figure 2 shows what said wondering (wandering?) inspired.

Figure 2 External junction temperature protection for the Q1 pass transistor. Since Q1’s internal junction temperature can’t be directly measured, it must be inferred from power dissipation, junction to ambient thermal resistance, and ambient temperature. If it tops 150 oC, A1d stops the show. 

What was needed was an external version of the now missing LM3x7’s internal junction overtemperature cutoff. Of course, the challenge with implementing an external junction temperature limiter is that internal transistor junctions are a second cousin to the classic Schrodinger’s cat.

Well, maybe not exactly. Unlike the famous quantum kitty, whose temperature (whether body or room) is theoretically unknowable. Junction temperature, while difficult to directly observe, might at least be calculated. 

And in fact, this is what the right-hand half of Figure 2 does. 

The necessary junction temp math is:

Tj = (Ij Vj)/Sja + Ta 

Where:

Tj	Junction temperature
Ij	Amperage through the junction
Vj	Voltage across the junction
Sja	Thermal conductivity (watts/degree) from junction to ambient from Q1 datasheet
Ta	Ambient temperature

The analog arithmetic

Figure 2’s circuitry performs analog arithmetic by relying on the nifty 17th-century invention of John Napier for multiplication and division: adding and subtracting logarithms. Here’s how the Figure 2 circuitry divides (and multiplies!) up the work.

Q3’s Vbe is the logarithm of the Q1 current programming signal sensed via R6. Meanwhile, Q4’s Vbe logs the voltage across Q1 monitored by Q8 and R6. 

Q3 and Q4 are connected in series, so their log voltages sum. About 400 years ago (now that’s really legacy technology!) Napier showed that adding logs is equivalent to multiplication. So, the sum of Vbe’s becomes the IjVj product term in the Tj math.

The IjVj signal is applied to A1c’s non-inverting input, which then subtracts Q5’s Vbe present on the inverting input. Because subtracting logs equates to division (thanks again, Johnny!), if R8 is properly scaled, this division provides the Sja normalization term for Rja. The quotient yields the log of junction temperature rise above ambient..

The antilog transistor Q6’s collector current, in concert with the R9/R10 network (at long last!) converts A1c’s output to a 2 mV/oC junction temperature signal. That’s summed by A1d with Q7’s ambient temperature signal.

When the sum bumps against Q1’s 150 °C safety limit, A1d’s output ramps positive, overriding the programmed source current to a safe value.

Which you might say is the cat’s meow. 

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Cross connect complementary current sources to reduce self-heating error
• Improve the accuracy of programmable LM317 and LM337-based power sources
• Calculator or Slide Rule?
• Special day for physicists’ cats
• Is that a banana in your pocket (or are you just glad to see me)?

The post Programmable current source with overtemperature shutoff appeared first on EDN.

Zoom is a display tool that expands the view of the selected waveform. The source trace can be expanded horizontally and vertically for detailed visual analysis or further processing. Each zoom trace can have its own horizontal and vertical scale setting, enabling views of the source trace using multiple horizontal and vertical scales. All digital oscilloscopes offer zoom functionality.

Zoom is important because oscilloscopes can acquire gigasamples of data per acquisition, with a vertical resolution of 12 or more bits. This data must be displayed on a screen with a resolution of approximately 1920 x 1080 pixels. If a full acquisition is displayed, the data has to be compacted to fit on the screen. Expanding the data with a zoom trace so that it fits within the screen resolution allows a view of all the acquired data.

Zoom demo

Zoom can be invoked from this oscilloscope’s front panel using the Zoom button. It can also be evoked interactively by touching the touchscreen and dragging the resulting box over the area to be expanded. Zoom traces can also be controlled from the Zoom Trace dialog boxes (Figure 1).

Figure 1 An example of several zoom instances used to analyze a remote keyless entry system waveform. The Zoom dialog box is used to control each zoom trace. Source: Art Pini

The source waveform from a remote keyless entry (RKE) system appears as trace M1 in the top grid. The waveform comprises an amplitude-modulated RF carrier. The modulation encodes the commands to lock a car door. Zoom is used to expand the fifth pulse in the acquired waveform horizontally. Note that the zoomed area is highlighted by increased intensity on the source trace. The expanded version appears in trace Z1 (second down from the top). The Z1 trace is controlled using the Z1 zoom dialog box at the bottom of the display.

The trace’s horizontal and vertical scale and offset can be adjusted interactively while observing the effects on the screen. The trace annotation box for the Z1 trace shows the vertical and horizontal scaling for the zoom trace. Trace Z1 has a horizontal scale of 150 microseconds per division, compared to the 5 milliseconds per division scale of the M1 source trace, representing an expansion of thirty-three times.

The zoom trace reveals variations in the RF carrier amplitude at the start and end of the burst. These keying transitions affect the generation of spurious signals that can interfere with other RF services. The zoom trace Z2 expands the view of the trailing edge of the first zoom trace and displays it in detail in the third grid from the top. Here, we have an example of Zoom on Zoom.

The analysis continues by demodulating the signal in Z2 by low-pass filtering the absolute value of the waveform. The demodulated signal can be measured to obtain the signal amplitude’s slew rate and the decaying amplitude’s time constant. This is an example of a math operation on Zoom. The math trace F1 performs demodulation; the result is displayed in the bottom grid. This example used two zooms, each with a different horizontal scale.

Horizontal and vertical scale factors

Zoom, in the oscilloscope used for this article, can be applied to any waveform, acquired signals, math, memory, or even other zoom traces. Zoom traces are waveforms like any other. They can be expanded further using another zoom trace, allowing the same signal to be viewed with multiple horizontal or vertical scale factors.

Math operators can be applied, allowing arithmetic, filtering, or FFTs to be performed on them. The number of available zoom traces generally matches the number of acquisition traces; however, all non-acquisition traces, like math or memory traces, have zoom functionality in this family of oscilloscopes.

Figure 2 provides an example of zoom being used to expand a signal vertically.

Figure 2 The echo in an ultrasonic range finder signal is expanded vertically to see the details of a double signal return. Source: Art Pini

A double echo in an ultrasonic range finder is zoomed vertically to see the detail of the waveform that is not easily discerned on the acquired waveform. The vertical resolution of this waveform is twelve bits or 4096 levels. At least a four-to-one vertical zoom is required to render the full resolution on a display with 1080-pixel vertical resolution. A ten-to-one vertical expansion shows the echo at 5 mV per division, providing a detailed view of the waveform structure.

Multi-Zoom

Some applications use multiple zoom traces with the same expansion factor for comparison purposes. Consider the measurement of an I2C data signal and clock signals shown in Figure 3.

Figure 3 Using time-locked multi-zoom to verify the timing between an I2C data and its associated clock signal. Source: Art Pini

The signal in the top grid is an I2C data signal. The grid immediately below that is the associated I2C clock. These waveforms are expanded synchronously using a feature called multi-zoom. Multi-zoom locks the selected zoom traces together. This feature allows common horizontal control of all zoom traces. They can be expanded or contracted synchronously, locked in time, or offset by a user-defined time offset.

In the example, the zoom traces Z1 and Z2 are the expansions of the data and clock signal, respectively. They are locked in time with no offset. The expanded view makes it easier to see the relative timing of the signals. So, the start condition, where the data signal is forced to a low state, followed by the clock signal being forced low, is easy to discern. The zoom traces incorporate the address field of the I2C packet. The expanded view afforded by the zoom displays is useful in evaluating physical layer issues like signal levels, period, with, transition times, and timing.

The multi-zoom feature also includes an auto-scroll mode to automatically scan through the entire waveform at a user-set rate (Figure 4).

Figure 4 The zoom auto-scroll controls allow automatic scrolling of the zoom horizontal location of the zoom trace to scan through long records. Source: Art Pini

Automatic scrolling is very helpful when moving narrow zoom windows through very long acquisitions that might require an extreme number of turns of a knob. It offers two scan rates and the ability to jump to the extreme values.

Comparing waveform segments

Zoom displays can help compare waveforms. For instance, an acquired I2C data signal contains multiple data packets; Zoom can be used to display these packets on the same expanded timescale for comparison (Figure 5).

Figure 5 Using zoom traces to separate and compare I2C data packets on the same expanded time scale. Source: Art Pini

Packets 1, 2, and 4 from the acquired I2C data bus acquisition are separated and compared using three zoom traces with the same scale factors but with different offsets. It is easy to see the difference in the length of packet 2; the data content of the three packets differs in the last half millisecond of the waveforms.

Using Zoom to window signals

Zoom can select, or window, specific regions of an acquired signal for further processing. This allows the examination of selected parts of a signal separately. Consider analyzing an RKE system that uses frequency shift keying (FSK) to encode commands (Figure 6).

Figure 6 Using zoom traces to isolate the one and zero state frequencies in an RKE system using FSK modulation. Source: Art Pini

The trace in the upper left grid represents 10 ms of a 260-ms-long RKE command. The RKE fob uses FSK to encode the digital one and zero states. The trace below the acquired trace shows that the demodulated FSK data is an NRZ serial signal. The upper-right grid shows the FFT of the acquired RKE signal. The signal has a frequency-modulated 434-MHz carrier. The FFT shows two peaks characteristic of frequency hopping, one corresponding to the frequency of the one state and the other to the frequency corresponding to the zero state.  

Zoom can be used to separate the parts of the acquired signal corresponding to the signal’s 0 and 1 states. Zoom trace Z1 (third grid down on the left) shows the part of the RKE signal matching the zero state shown in the demodulated signal. The duration of the zoom trace is adjusted to fit within the duration of the digital state.

Similarly, the zoom trace Z2 (bottom left) has been used to select the part of the signal in the one-state. The intensified segments on the acquired waveform correspond to the selected regions. FFTs of the zoom traces show that each digital state contributes a specific frequency to the signal.

Measurement parameters identify the zero frequency as 433.888 MHz and the one state as 433.964 MHz. The magnitude of the frequency shift between the two digital states is determined by taking the difference between the two measured frequencies, which is 76 kHz. Zoom has separated the frequencies associated with each digital state.

Note that the FFT’s frequency resolution is proportional to its input’s record length and that the zoom traces are shorter than the acquired waveform and thus will have poorer resolution. This does not matter in this example, where the goal is to determine the frequencies of the two digital states.

Expanding waveforms with zoom

Zoom is a useful tool for studying and analyzing acquired waveforms by providing an expanded view of the signal vertically or horizontally. These traces provide enhanced visual acuity, allowing the instrument’s full amplitude and time resolution to be displayed on the screen. They also select specific parts of a signal, allowing for the analysis of only those portions of the signal that are of interest.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

 Related Content

• 10 tricks that extend oscilloscope usefulness
• Oscilloscope special acquisition modes
• Closing the gaps in your digital oscilloscope waveforms
• Basic oscilloscope operation

The post Using an oscilloscope’s zoom functions appeared first on EDN.

AquiSense Inc of Erlanger, KY, USA (which designs and makes UV-C LED water disinfection systems) says that its Pearl Aqua Kilo full-scale UV-C LED product has been awarded NSF/ANSI/CAN 61-2024 certification and completed the validation process required by the US Environmental Protection Agency (EPA) UV Disinfection Guidance Manual (UVDGM), providing water utilities and industrial users with a new, highly effective tool for protecting public health...

In light of the soft market environment and negative FX effects, deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany is adjusting its forecast for 2025...

Kyocera AVX releases the KGP Series of commercial-grade stacked capacitors targeting high-frequency applications in the industrial and downhole oil and gas industries. The new stacked MLCCs deliver higher capacitance values in the same mounting area as traditional capacitors to support miniaturization.

(Source: Kyocera AVX)

These stacked capacitors are manufactured without lead or cadmium to support sustainability and ease standards compliance. They also provide low equivalent series resistance (ESR) and inductance (ESL), minimizing noise and optimizing performance, and feature metal lead frames that reliably suppress thermal and mechanical stress for greater stability and durability. Applications extend throughout the industrial, alternative energy, and downhole oil and gas industries, and include power supplies, DC/DC converters, control circuits, high-voltage coupling, and DC blocking.

The KGP Series stacked MLCCs, in C0G, X7R, and X7T dielectrics, are available in five EIA case sizes (1210, 1812, 1825, 2220, and 2225) with two stack sizes (maximum thicknesses spanning 3.40 to 6.95 mm), and “J” or “L” leads. Key specs include operating voltages ranging from 50 V to 1,500 V, capacitance values ranging from 10 nF to 47 µF ±10% or 20% tolerance, and an operating temperature range from -55°C to 125°C.

The stacked MLCCs with C0G and X7R dielectrics are available in all five EIA case sizes with the full range of rated voltage values and capacitance values up to 220 nF and 47µF, respectively. MLCCs with X7T dielectrics are available in three EIA case sizes (1210, 1812, and 2220) with three rated voltages (250 V, 450 V, and 630 V), and capacitance values up to 4.7 μF.

These ceramic capacitors are tested for a range of factors to ensure performance in challenging high-frequency applications. These include visual characteristics, capacitance values, dissipation factor, temperature coefficient, insulation resistance, dielectric strength, temperature cycling, steady state and load humidity, high temperature load, termination strength, bending, vibration resistance, and soldering heat resistance. They are RoHS compliant and packaged for automated placement on tape and reel in quantities of 500–1,500. 

The post Stacked MLCCs support miniaturization appeared first on EDN.

Silicon Labs launches its Simplicity Ecosystem, a suite of modular software tools that are designed to simplify embedded IoT development. The Simplicity Ecosystem centers around Simplicity Studio 6 with the upcoming Simplicity AI SDK framework, available in 2026. The ecosystem brings together installation, configuration, debugging, and analysis into a single developer-first environment.

“The Simplicity Ecosystem represents a major step in making intelligent, context-aware development a reality,” said Manish Kothari, senior vice president of software development, Silicon Labs, in a statement. “By integrating AI into every layer of our tools, we will give developers a platform that learns, adapts, and accelerates innovation across the entire IoT lifecycle.”

The new Simplicity Ecosystem extends that legacy of the Simplicity Studio, available for more than a decade, by breaking the toolchain into modular, interoperable components. These components fit seamlessly into modern workflows, whether they are GUI-based or automated, and can work independently or as part of the ecosystem.

The Simplicity AI SDK will allow developers to chat with their code through new AI-powered integrations. (Source: Silicon Labs)

The core tools include the Simplicity installer for on-demand installation of SDKs, examples, and tools; VS code and CLI integration; device manager for a unified interface for identifying, managing, and programming Silicon Labs hardware; Simplicity commander, a command-line for programming, debugging, and security configuration; a network analyzer protocol-aware tracing tool for wireless traffic, with real-time visibility into packet exchanges across Bluetooth LE, Zigbee, Thread, and Matter networks; and the energy profiler real-time measurement tool that correlates energy consumption directly to code execution. It also includes a full suite of configuration, control/debug, and analysis tools for all wireless technologies.

The software tools ecosystem supports Silicon Labs Series 2 and Series 3 devices and major IoT standards, including Bluetooth LE, Zigbee, Thread, Matter, Wi-Fi, Wi-SUN, and Z-Wave.

The Simplicity AI SDK  framework will enable an AI-augmented workflow, supporting engineers  by acting as a collaborator that interprets code, surfaces insights, and assists with tasks across the lifecycle from project setup to field debugging. It combines context awareness and intelligent automation to accelerate development.

The first release will integrate with VS code to let developers “chat with their code,” marking a shift toward AI-assisted design, Silicon Labs said. It can explain functions, trace errors, and suggest improvements in real time, using an understanding of project context and Silicon Labs SDKs.

Dynamic context engineering is at the heart of Simplicity AI SDK, the company added, giving AI agents the right data at the right time to understand project structure, interpret documentation, and provide contextual support without manual lookup.

The Simplicity AI SDK will be available in 2026, beginning with developer feedback and beta testing. You can join the Simplicity AI SDK early access waitlist. Future updates will extend these capabilities across Silicon Labs’ tools, enabling adaptive debugging, optimization, and application generation. Simplicity Studio 6 is available now for download.

The post Software tools deliver smarter IoT development workflows appeared first on EDN.

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and developed and previously manufactured high-power industrial blue lasers — has entered into a strategic framework agreement with Nuburu Defense LLC and Maddox Defense Inc of San Diego, CA, USA to establish a joint venture...

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has appointed Matthias Buchner as senior VP of global sales & chief marketing officer, effective 1 December. He will report directly to chief executive officer Robert Feurle...

An EDN Design Idea (DI) presented a discussion of how to increase the resolution of an ADC by adding a non-deterministic, zero-mean, Gaussian noise dither waveform to a signal to be converted; then, oversampling the sums, and low-pass filtering (thereby averaging) the ADC conversions. (As noted, a filter that optimally removes out-of-band high-frequency dither noise is generally more complex than a simple averager.)

Wow the engineering world with your unique design: Design Ideas Submission Guide

Conversions are executed at a rate of M times that are required to satisfy the Nyquist condition. Low-pass filtering them offers an increase in resolution of a factor of M and of B = log2(M) bits.

The signal at the filter output has negligible energy above the Nyquist frequency, and so only every Mth output of the filter needs to be sampled in a process known as decimation. Even though the resolution of the conversions has been increased by a factor of M, the signal-to-quantization noise ratio has not improved by the same amount. Because there is still non-deterministic noise present below the Nyquist frequency, it turns out that the signal-to-quantization noise ratio has improved only by a factor of sqrt(M) and by sqrt(B) bits.

Avoiding dither-associated noise

But what if the signal were DC and the dither were known, deterministic, and repeated every M samples? The addition of dither-associated noise could be avoided if a judiciously selected dither waveform were added to the signal to be converted and its mean subtracted from the average of M conversions. A simple averager would suffice for the filter. (And if the dither were zero-mean, there would be nothing to subtract!) The advantage of this approach would be that the signal-to-quantization noise ratio would be improved by the same amount as the resolution.

So, what might constitute a “judiciously selected” dither waveform? I won’t keep you in suspense: a sawtooth whose peak-to-peak amplitude is an odd integral multiple of the size of the least significant bit (LSB) of the ADC fits the bill. Why only “odd”? Let’s see why the odds work and why the evens are not as good choices.

Examining the effects of dithering

In examining the effects of dithering, it’s convenient to work with integer values. For example, let’s assign the smallest possible ADC conversion step size value not to 1 as is traditional, but to M, which is also the number of conversions to be averaged to produce an output. Consider the case of M equal to 64.

Accordingly, all ADC conversions are integral multiples of M: 0, 64, 128, etc., whereas the dither ramp takes on the values of d = 0, 1, 2… 63. Each dither value is added to an input value of (for example) 42, and each sum is converted.

There will be 42 conversions of value 64, and 22 conversions of value 0. The average is 42. We have our increase in resolution! This works for input signals of 0, 1, 2… and up to and well beyond 63.

It’s limited only by the input conversion range of the ADC. Notice that some very large input signals, which by themselves are within that conversion range, will, when added to portions of the dither waveform, be moved above that range. In such cases, the averaging process will yield incorrect results. These input values are in the “dither-disadvantaged” range.

For dither to be of value, it must be added to the signal prior to A-to-D conversion; that is, the dither is an analog signal. But analog or digital, a question arises as to its optimal peak-peak range. Should it take on exactly the values discussed above? Or should each of these values be multiplied by some number? An Excel program was written to answer this question by examining sets of signals plus dither of the form of Expression (1):

S + si + dk  · Aa  (1)

Table 1 describes each variable.

S	Any arbitrary multiple of M = 64 such that Expression (1) is entirely within the ADC conversion range
si = i, where i = 0, 1, 2… 63	Where S + si constitute a set of input signals
dk = k – 31.5, where k = 0, 1, 2… 63	Where the -31.5 renders dither dk zero-mean, but requires a compensatory value of 31.5 to be added to the average of sets of M ADC conversions
Aa = a/10, where a = 7, 8, 9… 70	Where Aa is the peak-peak value of the dither in units of 1 LSB

Table 1: The variables in Expression (1) that an Excel program was built around to examine sets of signals plus dither.

Expression (1) is evaluated for the full range of si for every given Aa. ADC conversions yielding multiples of 64 are determined for each value of dk.

These conversions are averaged, added to 31.5, and the sum converted to an integer. The number of errors ei,a (0, 1, 2…) in units of 1/64 of an LSB are determined by subtracting this result from S + si.

The errors are then graphed against si for each peak-peak dither amplitude Aa.

This eye chart appears in Figure 1. Confusing, impressive, or both, it’s difficult to get too much useful information out of it. But it’s clear that even though there are errors in most cases, their magnitudes are small compared to the resolution of a single ADC conversion; useful resolution enhancement has been achieved.

Figure 1 An eye chart with the errors of dithered input signals of amplitudes 0 to 63 for and ADC whose LSB is 64.

Additional calculations

To derive more useful information so that the best values of Aa can be identified, some additional calculations are performed. For each Aa, the ei,a are squared, summed over all i, and the square root of the average of the sum is taken to produce the rms error erms. This provides a figure of merit for each scaled peak-peak range Aa of dither. erms is graphed against Aa in Figure 2.

Figure 2 The RMS errors of all input signals with dither added, providing a figure of merit for each scaled peak-peak range Aa of dither.

What is clear from this graph is that zero errors can be obtained if the peak-to-peak dither amplitude is an odd multiple of the ADC conversion LSB. To understand why this happens, consider multiplying dither elements -31.5, -30.5… 31.5 by an odd integer and taking the modulo M = 64 portion of the products.

Surprisingly, you’ll find every number in the basic dither sequence of 0, 1, 2… 63. This gives full coverage to every possible value of input S + si. But why aren’t even multiples error-free?

The modulo 64 of products with even integer multiplicands are even numbers only; the odd elements of the basic sequence are missing. And when Aa is not an integer, the rms errors are generally (although not always) even larger. It could be challenging to generate an analog signal whose range is an exact odd multiple. To minimize the error due to an inexact dither amplitude, we might skip the choice of Aa equal to 1 and choose a multiplier of 3 or 5.

A dither generator

A suitable circuit for generating and using a non-zero mean dither waveform is shown in Figure 3.

Figure 3 A suitable circuit for generating a non-zero mean dither waveform.

At the start of a string of conversions, d2 is set to 0 V to disable M1 while d1 is connected to a reference voltage Vref, such as the one used by the ADC. This allows C1 to begin to charge.

After the last conversion, d1 is left open or grounded, and d2 is set high to enable the MOSFET and quickly discharge the capacitor. Because the peak value of the dither voltage is such a small portion of Vref, what would normally be a signal involving a negative exponent of time is well-approximated as a linear ramp of:

Vref · t / T, where T = R1 · C1

Assuming that the M conversions are equally spaced in time and last for Tsam seconds, T is selected so that the desired Aa is equal to:

Aa = Vref · Tsam / T

The intended signal is obviously not zero-mean. And there is also a small amount of charge injection into C1 when the MOSFET shuts off due to that device’s parasitic capacitances. (A MOSFET with minimal capacitances and a fairly large C1 will work together to limit the size of the charge injection voltage offset.)

Fortunately, even a simple calibration scheme that converts known small and large signals and fashions a best-fit linear correction out of these renders the offsets inconsequential. Note that the dither waveform is subtracted from rather than added to the input signal. This means that the smallest rather than the largest input signals that alone would be within the ADC conversion range are now the ones in the dither-disadvantaged range. If this is of concern, The R resistor connected to ground in Figure 3 can be replaced with a resistor divider presenting the same resistance as R and driven by Vref. A small division ratio is chosen to ensure that all ADC inputs are positive. This returns the dither-disadvantaged range to the larger of all possible ADC conversions. 

Errors

The increase in resolution should not be confused with improvements in accuracy; no ADC is ideal. All have integral and differential non-linear errors.

Dither-related ADC improvements

A means has been presented of generating a dither waveform and employing a method using it to enhance the resolution and signal-to-quantization noise of ADC conversions by a factor M, where M is the number of conversions per sample of a DC input signal. A simple calibration technique is required involving the use of ADC conversions of known small and large signals to afford gain and offset error compensation. It should be noted that the application of dither to increase ADC resolution is still, to some extent, at the mercy of the ADC’s accuracy.

Blue sky possibilities

If we wish to consider AC input signals rather than only DC ones, it would be possible to digitally subtract the dither value associated with each conversion from that conversion. Perhaps an averager would still suffice as the filter, perhaps not. Perhaps overall performance improvement would not be as good as with a DC signal, or maybe it would. I’ll do some further analysis, but I also invite comments on the matter. 

With AC signals, we don’t have the luxury of waiting for the capacitor in the sawtooth generator to discharge; sampling should be at an uninterrupted, constant rate. Instead of a sawtooth, a triangle wave of the same peak-to-peak amplitude would work.

It could be created with a square wave driving an R1-C1 lowpass filter whose output is capacitively coupled to the unity gain op amp input of Figure 3 in place of the sawtooth generator.

This input would be referenced through a large resistor to ground or to a DAC voltage within the op-amp’s common-mode input range. Dither-disadvantaged ranges might now exist at both extremes of the ADC conversion range. Dealing with such ranges was discussed with sawtooth dither, and the same method can be employed with the triangular waveform. Successive sets of M conversions would occur on rising and on the falling ramps of the triangle wave. The triangular dither waveform would work with DC signals, too, and has the advantage of eliminating MOSFET charge injection.

But with or without a dither waveform, annoying artifacts can arise whenever there is correlation between the periods of the conversion rate and the AC input signal. It is expected that with the dither discussed, artifacts would be M times smaller than without dither.

A known solution to the artifacts problem is to add a small, random analog dither waveform. This will, of course, have a negative impact on signal-to-quantization noise, but the tradeoff may be worth it. I suspect that the magnitude of the new dither should be the size of the ADC’s LSB, but once again, I will investigate, and I do invite comments.

Acknowledgements

I’d like to acknowledge significant contributions to the development and readability of this DI by someone who wishes to remain anonymous.

 Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

 Related Content

• Increasing bit resolution with oversampling
• Frequency dithering enhances high-performance ADCs
• Dithering increases dynamic range in digital-radio system
• Analyzing ADC Noise Impacts on Wireless System Performance

The post Increasing ADC resolution by adding dither to DC signals appeared first on EDN.

Highlighting how light-based technology is helping to power the UK’s economic growth, on 3 October CORNERSTONE Photonics Innovation Centre (C-PIC) — the UK’s dedicated Innovation and Knowledge Centre (IKC) for silicon photonics (affiliated with the University of Southampton and the University of Glasgow, as well as the UK government’s Science and Technology Facilities Council) — was visited by Prince Edward, His Royal Highness The Duke of Edinburgh, who met academics developing silicon photonics and saw how this technology is being used in data centers, as well as its emerging applications in healthcare, AI and quantum technology...

The automotive industry is continuing its transition from proprietary automotive serializer/deserializer (SerDes) solutions to an interoperable ecosystem established by the Automotive SerDes Alliance and its first open-standard ASA Motion Link (ASA-ML). ASA-ML is now being implemented by OEMs and Tier 1 suppliers because it provides an asymmetric high-speed communications standard that connects the increasing number of cameras, sensors and displays used in In-Vehicle Networking. Microchip Technology announced a significant milestone with AVIVA Links, an automotive company delivering advanced multi-Gigabit vehicle infrastructure for ADAS and IVI systems, demonstrating that ASA-ML chipsets from multiple vendors can interoperate seamlessly to deliver scalable, high-speed connectivity. This interoperability between major semiconductor suppliers underscores the viability of the ASA-ML ecosystem and its growing role in the automotive industry.

The Automotive SerDes Alliance has more than 175 members, including OEMs such as BMW, Ford, GM, Hyundai Kia Motor Company, Nio, Renault/Ampere, Stellantis, Volvo and Xiaopeng Motors. The multi-vendor ecosystem is actively collaborating to bring ASA-ML enabled systems to the market, addressing the rapid growth of Advanced Driver Assistance Systems (ADAS) and In-Vehicle Infotainment (IVI) applications.

“Microchip is a market leader in automotive networking and connectivity, and achieving robust ASA-ML interoperability with AVIVA Links—who has announced a pending acquisition by NXP—is a pivotal moment for the Automotive SerDes Alliance and a clear signal to the market,” said Kevin So, vice president of Microchip’s communications business unit. “This collaboration highlights the benefits of a multi-source, open standards approach and gives automotive OEMs and Tier 1 suppliers the confidence to design their next-generation ADAS architectures around ASA-ML, knowing they have a scalable, robust and secure connectivity standard backed by leading semiconductor suppliers.”

The ASA-ML standard supports asymmetric high-speed video, control and data transmission up to 16 Gbps, offering a scalable and forward-looking solution. To achieve ADAS L2 and L2+ autonomous-level applications, an increasing number of cameras and sensors must be added into vehicles. These applications require the ASA-ML standard’s scalability, architectural flexibility and interoperability benefits, further driven by the availability of multi-vendor, high-bandwidth connectivity solutions that reduce reliance on proprietary solutions.

“AVIVA Links is focused on delivering advanced connectivity and enabling standards-based, interoperable solutions for the next generation of automotive systems,” said Kamal Dalmia, CEO of AVIVA Links.  “Proving interoperability with Microchip’s ASA-ML SerDes chipset is an important milestone for the automotive industry, and together with our pending acquisition by NXP, will further drive confidence in ASA-ML adoption at OEMs and Tier 1s.”

The post Microchip and AVIVA Links Achieve ASA-ML Interoperability, Accelerating Open Standards for Automotive Connectivity appeared first on ELE Times.

STMicroelectronics and SP Group (SP) have commenced operations for Singapore’s largest industrial district cooling system at STMicroelectronics’ (ST) Ang Mo Kio TechnoPark. The event was inaugurated by Ms. Low Yen Ling, Senior Minister of State, Ministry of Trade and Industry and Ministry of Culture, Community and Youth.

The system is expected to reduce carbon emissions by up to 120,000 tonnes per year and enable 20 per cent savings on cooling-related electricity consumption. It will also repurpose over half a million cubic meters of water each year by using reject reverse osmosis water, previously used in ST Cooling Towers, to support the new district cooling operations.

This marks ST’s first use of district cooling at a manufacturing facility and will strengthen ST’s commitment to be carbon neutral by 2027.

“The deployment of Singapore’s largest industrial district cooling system at our Ang Mo Kio TechnoPark demonstrates our commitment to pioneering energy-efficient solutions that reduce carbon emissions and conserve resources. This achievement strengthens our partnership with Singapore in advancing its national sustainability goals,” said Rajita D’Souza, President of Human Resources and Corporate Social Responsibility at STMicroelectronics. “By integrating advanced technologies like the district cooling system, we are driving a smarter, more sustainable future — showcasing how industry leadership and environmental stewardship align to create lasting value for our business, communities, and the planet.”

“SP Group’s strategic partnership with STMicroelectronics marks a pivotal milestone in our nation’s transition towards a low-carbon future. This project showcases how collaborative innovation can transform urban infrastructure to deliver sustainable, energy-efficient solutions. District cooling will continue to play a vital role in Singapore’s net-zero ambitions, enabling carbon emissions reduction and enhancing energy resilience across industrial and urban developments,” said Stanley Huang, SP’s Group Chief Executive Officer.

Technical details of the district cooling system

Designed, built, owned, and operated by a joint venture between SP and Daikin Airconditioning (Singapore), the system has an installed capacity of up to 36,000 refrigeration tonnes (RT). It delivers continuous chilled water to cool both manufacturing and office spaces via a centralized closed-loop pipe network replacing individual chillers in each building. The total area served by the system is approximately 90,000 square metres.

Chillers in series counterflow configuration reduce the energy required to cool the water. This ensures an efficient and reliable 24/7 operation, with remote monitoring capabilities augmenting the operations team on site to come.

“This partnership with SP reflects Daikin’s commitment to delivering advanced, energy-efficient solutions that go beyond immediate operational needs. Our goal is to contribute to a more sustainable built environment, where technology plays a key role in enhancing resilience, reducing environmental impact, and supporting Singapore’s long-term climate ambitions,” said Chua Ban Hong, Managing Director at Daikin Airconditioning (Singapore).

Additionally, the new installations free up around 4,000 square meters of space at Ang Mo Kio TechnoPark, which will enable ST to install other equipment contributing to environmental impact mitigation. This includes perfluorocarbon (PFC) abatement equipment, with near-future plans for additional water reclamation systems and volatile organic compounds (VOC) abatement as part of its ongoing sustainability efforts.

The post Singapore’s largest industrial district cooling system begins operations to support ST’s decarbonization strategy appeared first on ELE Times.

Bluetooth Low Energy, Thread, Matter and proprietary protocols come together in a secure, feature-rich platform for supporting evolving standards, interface needs and market demands

As connectivity standards and market needs evolve, upgradeability has become essential for extending device lifecycles, minimizing redesigns and enabling differentiated features. To solve this challenge, Microchip Technology has released the highly integrated PIC32-BZ6 MCU that serves as a common, single-chip platform to reduce development cost, complexity and time-to-market for multi-protocol products featuring advanced connectivity and scalability.

“The PIC32-BZ6 MCU stands out for its powerful blend of connectivity, integration and flexibility in a single-chip solution,” said Rishi Vasuki, vice president of Microchip’s wireless solutions business unit. “Few devices bring together this breadth of features in a single chip, and we’re already seeing strong tremendous early adopter activity. Customers are leveraging its multi-protocol wireless capabilities, advanced analog features and high I/O to develop smarter, more connected products with greater efficiency.”

RF design for smart devices has become increasingly complex, and wireless solutions typically require multiple chips to add new features or frequent redesigns to support evolving industry standards. The PIC32-BZ6 MCU replaces these multi-chip solutions and reduces the redesign burden with a single, highly integrated chip that removes the complexity of multi-protocol wired and wireless connectivity. The MCU also includes analog peripherals to simplify motor control development, along with touch and graphics capabilities for advanced user interfaces and enhanced memory to support complex applications, heavy workloads and Over the Air (OTA) firmware updates.

The PIC32-BZ6 MCU platform streamlines development of products in the smart home and for automotive connectivity, industrial automation and wireless motor control use cases. Key features include:

• High memory and scalable package choices to support demanding applications and OTA updates: The high-performance MCU includes 2 MB Flash memory and 512 KB RAM and is available in 132-pin ICs and modules with additional pin and package variants planned.
• Multi-protocol wireless networking: Qualified against Bluetooth Core Specification 6.0, the device also supports 802.15.4-based protocols such as Thread and Matter plus proprietary smart-home mesh networking protocols.
• Design flexibility that extends product options and scaling opportunities: Versatile and comprehensive selection of on-chip peripherals goes beyond wireless connectivity and OTA updates to support:

Wired connectivity: Multiple interfaces include two CAN-FD ports for automotive and industrial communication, a 10/100 Mbps Ethernet MAC for high-speed wired connectivity and a USB 2.0 full-speed transceiver for seamless data transfer and PC integration.

Touch and graphics: Incorporate peripherals that enable advanced user interfaces including Capacitive Voltage Divider (CVD)-based touch capabilities with up to 18 channels.

Motor control: Simplifies system development through advanced analog peripherals such as 12-bit ADCs, 7-bit DAC, analog comparators, PWMs and QEI for precise motor position and speed control.

• Security by design to protect applications and IP: Includes immutable secure boot in ROM and an advanced on-board hardware-based security engine supporting AES, SHA, ECC and TRNG encryption.
• Reliability in harsh environments: The device is qualified to AEC-Q100 Grade 1 (125 °C) specifications for automotive and industrial environments.

The post Microchip Adds Integrated Single-Chip Wireless Platform for Connectivity, Touch, Motor Control appeared first on ELE Times.

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has announced the availability of a high-efficiency, high-power-density 5kWAC-to-48VDC reference design that demonstrates the full potential of GaN technology for next-generation server and AI power architectures...

Fabless firm Cambridge GaN Devices Ltd (CGD) — which was spun out of the University of Cambridge in 2016 to design, develop and commercialize power transistors and ICs that use GaN-on-silicon substrates — is working GlobalFoundries of Malta, NY (GF, the only US-based pure-play foundry with a global manufacturing footprint, including facilities in the USA, Europe and Singapore). The partnership strengthens CGD’s fabless strategy, expanding the supply chain for its ICeGaN power devices...

Alcoa Corp (which provides bauxite, alumina and aluminium products) has welcomed the announcement of the USA and Australian governments to advance the development of a gallium plant to be co-located at its Wagerup alumina refinery in Western Australia...