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High-bandwidth memory (HBM) is again in the limelight. At GTC 2025, held in San Jose, California, from 17 to 21 March, SK hynix displayed its 12-high HBM3E devices for artificial intelligence (AI) servers. The Korean memory maker also showcased a model of its 12-high HBM4, currently under development, claiming that it’s now completing the preparatory works for large-scale production of the 12-high HBM4 in the second half of 2025.

Micron, another leading memory supplier, is signaling strong demand for its HBM chips in AI and high-performance computing (HPC) applications. Micron’s chief business officer, Sumit Sadana, told Reuters that all of Micron’s HBM chips are sold out for the calendar year 2025.

Figure 1 HBM is creating a new “near memory” space between cache and main memory. Source: IDTechEx

HBM—essentially a 3D structure of vertically stacked DRAM dies on top of a logic die—relies on advanced packaging technologies like through silicon vias (TSVs) while using a silicon interposer for interconnection with the processor. It’s proving highly suitable in parallel compute environments such as HPC and AI workloads.

That’s because it can handle multiple memory requests simultaneously from various cores in GPUs and AI accelerators to facilitate parallel workload processing. In fact, HBM has become the main venue for overcoming memory bottlenecks in data-intensive HPC and AI workloads. Otherwise, these memory bottlenecks lead to underutilization of AI processors.

What’s also pivotal about HBM devices is their continued development to improve AI accelerator performance. For instance, the current generation HBM3E devices use thermal compression with micro-bumps and underfills to stack DRAM dies. Next, HBM makers like Micron, Samsung and SK hynix are transitioning toward HBM4 devices, which employ advanced packaging technologies such as copper-copper hybrid bonding to increase input/outputs, lower power consumption, improve heat dissipation, and reduce electrode dimensions.

Market research firm IDTechEx’s report “Hardware for HPC, Data Centers, and AI 2025-2035: Technologies, Markets, Forecasts” assesses the key developments and trends in HBM devices serving AI and HPC workloads. It also projects that compared to 2024, the unit sales of HBM are forecast to increase 15-fold by 2035.

Figure 2 The booming AI and HPC hardware is forecast to increase HBM sales 15-fold by 2035. Source: IDTechEx

HBM was a prominent technology highlight in 2024 for its ability to overcome the memory wall for AI processors. With the emergence of HBM4 memory devices, that trend is likely to continue in 2025 and beyond.

Related Content

• HBM Flourishes, But HMC Lives
• AI boom and the politics of HBM memory chips
• Memory Bottlenecks: Overcoming a Common AI Problem
• HBM memory chips: The unsung hero of the AI revolution
• High-bandwidth memory (HBM) options for demanding compute

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Due to their versatility, ease of design, and low cost, flyback converters have become one of the most widely used topologies in power electronics. Its structure derives from one of the three basic topologies—specifically, buck-boost topology. However, unlike buck-boost converters, flyback topologies allow the voltage output to be electrically isolated from the input power supply. This feature is vital for industrial and consumer applications.

Among the different control methods used to stabilize power converters, the most widely used control method is peak current mode, which continuously senses the primary current to provide important protection for the power supply.

Additionally, to obtain a higher design performance, it’s common to regulate the converter with the output that has the highest load using a technique called cross-regulation.

This article aims to show engineers how to correctly design the control loop that stabilizes the flyback converter in order to provide optimal functionality. This process includes minimizing the stationary error, increasing/decreasing the bandwidth as required, and increasing the phase/gain margin as much as possible.

Closed-loop flyback converter block diagram

Before making the necessary calculations for the controller to stabilize the peak current control mode flyback, it’s important to understand the components of the entire closed-loop system: the converter averaged model and the control loop (Figure 1).

              Figure 1 Here is how the components look in the entire closed-loop system. Source: Monolithic Power Systems

The design engineer’s main interest is to study the behavior of the converter under load changes. Considering a fixed input voltage (VIN), the open-loop transfer function can be modeled under small perturbations produced in the duty cycle to study the power supply’s dynamic response.

The summarized open-loop system can be modeled with Equation 1:              (1)

Where G is the current-sense gain transformed to voltage and GC(s) and GCI(s) are the transfer functions of the flyback converter in terms of output voltage and magnetizing current response (respectively) under small perturbations in the duty cycle. GαTS is the modeling of the ramp compensation to avoid the double-pole oscillation at half of the switching frequency.

Flyback converter control design

There are many decisions and tradeoffs involved in designing the flyback converter’s control loop. The following sections of the article will explain the design process step by step. Figure 2 shows the design flow.

Figure 2 The design flow highlights control loop creation step by step. Source: Monolithic Power Systems

Control loop design process and calculations

Step 1: Design inputs

Once the converter’s main parameters have been designed according to the relevant specifications, it’s time to define the parameters as inputs for the control loop design. These parameters include the input and output voltages (VIN and VOUT, respectively), operation mode, switching frequency (fSW), duty cycle, magnetizing inductance (LM), turns ratio (NP:NS), shunt resistor (RSHUNT), and output capacitance (COUT). Table 1 shows a summary of the design inputs for the circuit discussed in this article.

Table 1 Here is a summary of design inputs required for creating control loop. Source: Monolithic Power Systems

To design a flyback converter compensator, it’s necessary to first obtain all main components that make the converter. Here, HF500-40 flyback regulator is used to demonstrate design of a compensator using optocoupler feedback. This device is a fixed-frequency, current-mode regulator with built-in slope compensation. Because the converter works in continuous conduction mode (CCM) at low line input, a double-pole oscillation at half of the switching frequency is produced; built-in slope compensation dampens this oscillation, making its effect almost null.

Step 2: Calculate parameters of the open-loop transfer function

It’s vital to calculate the parameters of the open-loop transfer function and calculate the values for all of the compensator’s parameters that can optimize the converter at the dynamic behavior level.

The open-loop transfer function of the peak current control flyback converter (also including the compensation ramp factor) can be estimated with Equation 2:

      (2)

Where D’ is defined by the percentage of time that the secondary diode (or synchronous FET) is active during a switching cycle.

The basic canonical model can be defined with Equation 3:              (3)

Note that the equivalent series resistance (ESR) effect on the output capacitors has been included in the transfer function, as it’s the most significant parasitic effect.

By using Equation 2 and Equation 3, it’s possible to calculate the vital parameters.

The resonant frequency (fO) can be calculated with Equation 4:

              (4)

After inputting the relevant values, fO can be calculated with Equation 5:              (5)

The right-half-plane zero (fRHP) can be estimated with Equation 6:              (6)

The q-factor (Q) can be calculated with Equation 7:              (7)

After inputting the relevant values, Q can be estimated with Equation 8:              (8)

The DC gain (K) can be calculated with Equation 9:              (9)

After inputting the relevant values, K can be estimated with Equation 10:              (10)

The high-frequency zero (fHF) can be calculated with Equation 11:

              (11)

It’s important to note that with current mode control, it’s common to obtain values well below 0.5 for Q. With this in mind, the result of the second-degree polynomial in the denominator of the transfer function ends up giving two real and negative poles. This is different from voltage-control mode or when there is a very large compensation ramp, which results in two complex conjugate poles.

The two real and negative poles can be estimated with Equation 12:              (12)

The new open-loop transfer function can be calculated with Equation 13:              (13)

The cutoff frequency (fC) can be estimated with Equation 14:              (14)

The following sections will explain how the frequency compensator design achieves power supply stability and excellent performance.

Step 3: Frequency compensator design

Once the open-loop transfer function is modeled, it’s necessary to design the frequency compensator such that it achieves the best performance possible. Because the frequency response of the above transfer function has two separate poles—one at a low frequency and one at a high frequency—a simple Type II compensator can be designed. This compensator does not need an additional zero, which is not the case in voltage-control mode because there is a double pole that produces a resonance.

To minimize the steady-state error, it’s necessary to design an inverted-zero (or a pole at the origin) because it produces higher gains at low frequencies. To ensure that the system’s stability is not impacted, the frequency must be at least 10 times lower than the first pole, calculated with Equation 15:

           (15)

Due to the ESR parasitic effect at high frequencies, it’s necessary to design a high-frequency pole to compensate for and remove this effect. The pole can be estimated with Equation 16:

(16)

On the other hand, it’s common to modify the cutoff frequency to achieve a higher or lower bandwidth and produce faster or slower dynamic responses, respectively. Once the cutoff frequency is selected (in this case, fC is increased up to 6.5 kHz, or 10% of fSW), the compensator’s middle-frequency gain can be calculated with Equation 17:           (17)

Once the compensator has been designed within the frequency range, calculate the values of the passive components.

Step 4: Design the compensator’s passive components

The most common Type II compensator used for stabilization in current control mode flyback converters with cross-regulation is made up of an optocoupler feedback (Figure 3).

Figure 3 Type-II compensator is made up with optocoupler feedback. Source: Monolithic Power Systems

The compensator transfer function based on optocoupler feedback can be estimated with Equation 18:          (18)

The middle-frequency gain is formed in two stages: the optocoupler gain and the adjustable voltage reference compensator gain, calculated with Equation 19:

(19)

It’s important to calculate the maximum resistance to correctly bias the optocoupler. This resistance can be estimated with Equation 20:     (20)

The parameters necessary to calculate RD can be found in the optocoupler and the adjustable voltage reference datasheets. Table 2 shows the typical values for these parameters from the optocoupler.

Table 2 Here are the main optocoupler parameters. Source: Monolithic Power Systems

Table 3 shows the typical values for these parameters from the adjustable voltage reference.

Table 3 The above data shows adjustable voltage reference parameters. Source: Monolithic Power Systems

Once the above parameters have been obtained, RD can be calculated with Equation 21:              (21)

Once the value of R3 is obtained (in this case, R3 is internal to the HF500-40 controller, with a minimum value of 12 kΩ), as well as the values for R1, R2, and RD (where RD = 2 kΩ), RF can be estimated with Equation 22:   (22)

Where GCOMP is the compensator’s middle frequency gain, calculated with Equation (17). GCOMP is used to adjust the power supply’s bandwidth.

Because the inverted zero and high-frequency pole were already calculated, CF and CFB can be calculated with Equation 23 and Equation 24, respectively.         (23)           (24)

Once the open-loop system and compensator have been designed, the loop gain transfer function can be estimated with Equation 25:           (25)

Equation 25 is based on Equation 13 and Equation 18.

It’s important to calculate the phase and gain margins to ensure the stability of power supply.

The phase margin can be calculated with Equation 26:          (26)

After inputting the relevant values, the phase margin can be calculated with Equation 27:          (27)

If the phase margin exceeds 50°, it’s an important parameter necessary to comply with certain standards.

At the same time, the gain margin can be approximated with Equation 28:            (28)

Equation 29 is derived from Equation 25 at the specified frequency:     (29)

In this scenario, the gain margin is below -10dB, which is another important parameter to consider, particularly regarding compliance with regulation specifications. If the result is close to 0dB, some iteration is necessary to decrease the value; otherwise, the performance is suboptimal. This iteration must start by decreasing the value of the cutoff frequency.

This complete transfer function provides stability to the power supply and the best performance made possible by:

• Minimizing steady-state error
• Minimizing ESR parasitic effect
• Increasing bandwidth of power supply up to 6.5 kHz

Final design

After calculating all the passive component values for the feedback loop compensator and determining the converter’s main parameters, the entire flyback can be designed using the flyback regulator. Figure 4 shows the circuit’s final design using all calculated parameters.

Figure 4 Here is how the final design circuit schematic looks like. Source: Monolithic Power Systems

Figure 5 shows the bode plot of the complete loop gain frequency response.

Figure 5 Bode plot is shown for the complete loop gain frequency response. Source: Monolithic Power Systems

Obtaining the flyback averaged model via small-signal analysis is a complex process to most accurate approximation of the converter’s transfer functions. In addition, the cross-regulation technique involves secondary-side regulation through optocoupler feedback and an adjustable voltage reference, which complicates calculations.

However, by following the four steps explained in this article, a good approximation can be obtained to improve the power supply’s performance, as the output with the heaviest load is directly regulated. This means that the output can react quickly to load changes.

Joan Mampel is application engineer at Monolithic Power Systems (MPS).

Related Content

• Power Tips: Compensating Isolated Power Supplies
• Details on compensating voltage mode buck regulators
• Power Tips #139: How to simplify AC/DC flyback design with a self-biased converter
• Modeling and Loop Compensation Design of Switching Mode Power Supplies, Part 1
• Modeling and Loop Compensation Design of Switching Mode Power Supplies, Part 2

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The XDP711-001 48-V digital hot-swap controller from Infineon offers programmable SOA current control for high-power AI servers. It provides I/O voltage monitoring with an accuracy of ≤0.4% and system input current monitoring with an accuracy of ≤0.75% across the full ADC range, enhancing fault detection and reporting.

Built on a three-block architecture, the XDP711-001 integrates high-precision telemetry, digital SOA control, and high-current gate drivers capable of driving up to eight N-channel power MOSFETs. It is designed to drive multiple MOSFETs in parallel, supporting the development of power delivery boards for 4-kW, 6-kW, and 8-kW applications.

The controller operates within an input voltage range of 7 V to 80 V and can withstand transients up to 100 V for 500 ms. It provides input power monitoring with reporting accuracy of ≤1.15% and features a high-speed PMBus interface for active monitoring.

Programmable gate shutdown for severe overcurrent protection ensures shutdown within 1 µs. With options for external FET selection, one-time programming, and customizable fault detection, warning programming, and de-glitch timers, the XDP711-001 offers flexibility for various use cases. Additionally, its analog-assisted digital mode maintains backward compatibility with legacy analog hot swap controllers.

The XDP711-001 will be available for order in mid-2025. For more information on the XPD series of protection and monitoring ICs, click here.

Infineon Technologies 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Qualcomm unveiled the Snapdragon G series, a lineup of three chips for advanced handheld, dedicated gaming devices. The G3 Gen 3, G2 Gen 2, and G1 Gen 2 SoCs support various play styles and form factors, enabling gamers to play cloud, console, Android, or PC games.

Snapdragon G3 Gen 3 is the first in the G Series to support Lumen, Unreal Engine 5’s dynamic global illumination and reflections technology, for Android handheld gaming. Gen3 Gen 3 offers 30% faster CPU performance, 28% faster graphics, and improved power efficiency over the previous generation. Wi-Fi 7 support reduces latency and boosts bandwidth.

Snapdragon G2 Gen 2 is optimized for gaming and cloud gaming at 144 frames/s, delivering 2.3x faster CPU performance and 3.8x faster GPU capabilities compared to G2 Gen 1. It also supports Wi-Fi 7 for faster, more reliable connections.

Snapdragon G1 Gen 2 targets a wider audience, supporting 1080p at 120 frames/s over Wi-Fi. Designed for cloud gaming on handheld Android devices, it boosts CPU performance by 80% and GPU performance by 25% for smooth gameplay.

Starting this quarter, OEMs like AYANEO, ONEXSUGAR, and Retroid Pocket will release devices powered by the Snapdragon G series. For more details on all three platforms, click here.

Qualcomm Technologies

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Microchip’s AVR SD entry-level MCUs feature built-in functional safety mechanisms and a dedicated safety software framework. Intended for applications requiring rigorous safety assurance, they meet ASIL C and SIL 2 requirements and are developed under a TÜV Rheinland-certified functional safety management system.

Hardware safety features include a dual-core lockstep CPU, dual ADCs, ECC on all memory, an error controller, error injection, and voltage and clock monitors. These features reduce fault detection time and software complexity. The AVR SD family detects internal faults quickly and deterministically, meeting Fault Detection Time Interval (FDTI) targets as low as 1 ms to enhance reliability and prevent hazards.

Microchip’s safety framework software integrates with MCU hardware features to manage diagnostics, enabling the devices to detect errors and initiate a safe state autonomously. The AVR SD microcontrollers serve as main processors for critical tasks such as thermal runaway detection and sensor monitoring while consuming minimal power. They can also function as coprocessors, mirroring or offloading safety functions in systems with safety integrity levels up to ASIL D/SIL 3.

Prices for the AVR SD microcontrollers start at $0.93 each in lots of 5000 units, with lower pricing for higher volumes.

AVR SD product page

Microchip Technology 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Nexperia has expanded its GaN FET portfolio with 12 new E-mode devices, available in both low- and high-voltage options. The additions address the demand for higher efficiency and compact designs across consumer, industrial, server/computing, and telecommunications markets. Nexperia’s portfolio includes both cascode and E-mode GaN FETs, available in a wide variety of packages, providing flexibility for diverse design needs.

The new offerings include 40-V bidirectional devices (RDS(on) <12 mΩ), designed for overvoltage protection, load switching, and low-voltage applications such as battery management systems in mobile devices and laptop computers. These devices provide critical support for applications requiring efficient and reliable switching.

Also featured are 100-V and 150-V devices (RDS(on) <7 mΩ), useful for synchronous rectification in power supplies for consumer devices, DC/DC converters in datacom and telecom equipment, photovoltaic micro-inverters, Class-D audio amplifiers, and motor control systems in e-bikes, forklifts, and light electric vehicles. The release also includes 700-V devices (RDS(on) >140 mΩ) for LED drivers and power factor correction (PFC) applications, along with 650-V devices (RDS(on) >350 mΩ) suitable for AC/DC converters, where slightly higher on-resistance is acceptable for the specific application.

To learn more about Nexperia’s E-mode GaN FETs, click here.

Nexperia

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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NVIDIA’s Spectrum-X and Quantum-X silicon photonics-based network switches connect millions of GPUs, scaling AI compute. They achieve up to 1.6 Tbps per port and up to 400 Tbps aggregate bandwidth. NVIDIA reports the switch platforms use 4x fewer lasers for 3.5x better power efficiency, 63x greater signal integrity, 10x higher network resiliency at scale, and 1.3x faster deployment than conventional networks.

Spectrum-X Photonics Ethernet switches support 128 ports of 800 Gbps or 512 ports of 200 Gbps, delivering 100 Tbps of total bandwidth. A high-capacity variant offers 512 ports of 800 Gbps or 2048 ports of 200 Gbps, for a total throughput of 400 Tbps.

Quantum-X Photonics InfiniBand switches provide 144 ports of 800 Gbps, achieved using 200 Gbps SerDes per port. Built-in liquid cooling keeps the onboard silicon photonics from overheating. According to NVIDIA, Quantum-X Photonics switches are 2x faster and offer 5x higher scalability for AI compute fabrics compared to the previous generation.

NVIDIA’s silicon photonics ecosystem includes collaborations with TSMC, Coherent, Corning, Foxconn, Lumentum, and SENKO to develop an integrated silicon-optics process and robust supply chain.

Quantum-X Photonics InfiniBand switches are expected to be available later this year. Spectrum-X Photonics Ethernet switches will be coming in 2026 from leading infrastructure and system vendors. Learn more about NVIDIA’s silicon photonics here.

NVIDIA

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Frequent design idea (DI) contributor Nick Cornford recently published a synergistic pair of DIs “A pitch-linear VCO, part 1: Getting it going” and “A pitch-linear VCO, part 2: taking it further.”

Wow the engineering world with your unique design: Design Ideas Submission Guide

The main theme of these articles is design techniques for audio VCOs that have an exponential (a.k.a. linear in pitch) relationship between control voltage and frequency. Great work Nick! I became particularly interested in the topic during a lively discussion (typical of editor Aalyia’s DI kitchen) in the comments section. The debate was about whether such a VCO could be built around the venerable 555 analog timer. Some said nay, others yea. I leaned toward the latter opinion and decided to try to put a schematic where my mouth was. Figure 1 is the result.

Figure 1 555 VCO discharges timing cap C1 completely to the negative rail via a Reset pulse.

The nay-sayers’ case hinged on a perceived inability of the 555 architecture to completely discharge the timing capacitor, C1 in Figure 1. They seemed to have a good argument because, in its usual mode of operation, the discharge of C1 ends when the trigger input level is crossed. This normally happens at one third of the supply rail differential and one third is a long way from zero! But it turns out the 555, despite being such an old dog, knows a different trick, it involves a very seldom used feature of this ancient chip: the reset pin 4.

The 555 datasheet says a pulse on reset will override trigger and also force discharge of C1. In Figure 1, R3 and C2 provide such a pulse when the OUT pin goes low at the end of the timing cycle. The R3C2 product ensures the pulse is long enough for the 15 Ω Ron of the Dch pin to accurately evacuate C1. 

And that’s it. Problem solved as sketched in Figure 2.

Figure 2 The VCO waveforms; reset pulses at the end of each timing cycle, and is triggered when Vc1 = Vcon, to force an adequately complete discharge of C1.

Figure 3 illustrates the resulting satisfactory log conformity (due mostly to my shameless theft of Nick’s clever resistor ratios) of the resulting 555. VCO, showing good exponential (linear in pitch) behavior over the desired two octaves of 250 to 1000 Hz.

Figure 3 Log plot of the frequency versus control voltage for the two-octave linear-in-pitch VCO. [X axis = Vcon volts (inverted), Y axis = Hz / 16 = 250 Hz to 1 kHz]

In fact, at the price of an extra resistor, it might be possible to improve linearity enough to pick up another half a volt and half an octave on both ends of the pitch range to span 177 Hz to 1410 Hz. See Figure 4 and Figure 5.

Figure 4 R4 sums ~6% of Vcon with the C1 timing ramp to get the improvement in linearity shown in Figure 5.

Figure 5 The effect of the R4 modification showing a linearity improvement. [X axis = Vcon volts (inverted), Y axis = Hz / 16]

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• A pitch-linear VCO, part 1: Getting it going
• A pitch-linear VCO, part 2: taking it further
• VCO using the TL431 reference
• Ultra-low distortion oscillator, part 1: how not to do it.
• How to control your impulses—part 1
• A two transistor sine wave oscillator

The post Can a free running LMC555 VCO discharge its timing cap to zero? appeared first on EDN.

This year during APEC, much of the focus on the show floor revolved around data center tech, with companies showcasing high-density power supply units (PSU), battery backup units (BBU), intermediate bus converters (IBC), and GPU solutions (Figure 1). 

Figure 1: Up to 12 kW Infineon PSU technology leverages a mixture of the CoolSIC, CoolMOS, and CoolGaN technologies. 

The motivation comes from the massive power demand increase that the generative AI, in particular, LLMs have brought on, shooting up the 2% of global power consumption from data centers to a projected 7% by 2030. This power demand originates from the shift from the more 120 kV (single-phase AC) stepped down to 48 V to 250-350 kV (three-phase AC) stepped down to 400 VDC rails attached to the rack and distributed from there (to switches, PSUs, compute trays, switch trays, BBUs, and GPUs).

Infineon’s booth presented a comprehensive suite of solutions from the “power grid to the core.” The BBU technology (Figure 2) utilizes the partial power converter (PPC) topology to enable high power densities (> 12 kW) using scalable 4 kW power converter cards.

Figure 2: Infineon BBU roadmap, using both Si and GaN to scale up the power density of the converters with high efficiencies. Source: Infineon

The technology boasts an efficiency of 99.5% using lower voltage (40 V and 80 V) switches to increase figure of merit (FOM) and yield efficiency gains. The solutions are aimed at meeting space-restrictions of modern BBUs that are outfitted with more and more batteries and hence less space for the embedded DC/DC converter.

Their latest generation of vertical power delivery modules feature a leap in GPU/AI card power delivery, offering up to 2 A/mm2. These improvements create massive space-savings on the already space-constrained AI cards that often require 2000 A to 3000 A for power-hungry chips such as the Nvidia Blackwell GPU.

Instead of being mounted laterally, or alongside the chip, these devices deliver power on the underside of the card to massively reduce power delivery losses. The backside mounting does come with its profile restraints; there is a max height of 5 mm to facilitate heatsink mounting on the other side of the board, so these modules must maintain their 4-mm height. 

The first generation of the dual-phase module featured the silicon device that sat on top of the substrate with integrated inductors and capacitors to achieve 1 A/mm2, or 140A max,  in a 10 x 9 mm package. This was followed by a dual-phase module that featured a 1.5 A/mm2, or 160 A max, improvement within 8 x 8 mm dimensions. Embedding the silicon into the substrate to have only one PCB is what contributed to the major space-savings in this iteration (Figure 4). 

Figure 4: The second generation of Infineon vertical power delivery modules mounted on the backside of GPU PCB deliver a total of 2000 A. An Infineon controller IC can also be seen providing the necessary voltage/current through coordination with the vertical power delivery modules and chip.

The third generation just released has brought on two more power stages for a quad-phase module for 2 A/mm2, or 280 A max, in the 10 x 9 mm space; doubling the current density of the first generation in the same space (Figure 5). 

Figure 5: Third generation of Infineon vertical power delivery modules are mounted on the backside of GPU PCB delivering a total of 2,000 A. 

Custom solutions can go beyond this, integrating more power stages in a single substrate. Other enhancements include bypassing the motherboard and direct-attaching to the substrate in the GPU since PCB substrate materials are lossy for signals with high current densities.

However, this calls for closer collaboration with SoC vendors that are willing to implement system-level solutions. High current density solutions are in the works with Infineon, potentially doubling the current density with another multi-phase module.

The Navitas booth also showed two form factors of PSUs: a common redundant power supply (CRPS) form factor and a longer PSU that meets open compute project (OCP) guidelines and compiled to the ORv3 base specification (Figure 6). The CRPS solution delivers 4.5 kW with two-stages including a SiC PFC end and GaN LLC and offers titanium level efficiency.

Figure 6: Typical rack is shown with RAM, GPU, PSUs, and airflow outlet with barrel fans. The PSUs conform to the CRPS and provide redundancy to encourage zero downtime in the event of transient faults, brownouts, and blackouts.

Hyperscalers or high performance compute (HPC) applications that utilize the OCP architecture can install PSUs in a row to centralize power in the rack. The Navitas PSU offered for this datacenter topology offers up to 8.5 kW with up to a 98% efficiency using a three-phase interleaved CCM totem pole SiC PFC and three-phase GaN LLC (Figure 7).

Figure 7: Navitas 8.5 kW PSU is geared toward hyperscalers using both Gen-3 Fast SiC and GaNSafe devices.

Aalyia Shaukat, associate editor at EDN, has worked in the design publishing industry for six years. She holds a Bachelor’s degree in electrical engineering from Rochester Institute of Technology, and has published works in major EE journals as well as trade publications.

Related Content

• Data center power meets rising energy demands amid AI boom
• Telecom/Datacom 48V: Have no fear; 400V is here
• Power Tips #139: How to simplify AC/DC flyback design with a self-biased converter
• Data center next generation power supply solutions for improved efficiency

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